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([2602:47:d49d:ec01:944b:63b7:13bc:4d26]) by smtp.gmail.com with ESMTPSA id n12-20020a170902d2cc00b0016c29dcf1f7sm13281112plc.122.2022.08.24.17.23.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 24 Aug 2022 17:23:46 -0700 (PDT) Message-ID: <7b4759db-6592-2bc2-25f6-a762e8a83c26@linaro.org> Date: Wed, 24 Aug 2022 17:23:44 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 04/17] target/i386: add ALU load/writeback core Content-Language: en-US To: Paolo Bonzini , qemu-devel@nongnu.org Cc: paul@nowt.org References: <20220824173123.232018-1-pbonzini@redhat.com> <20220824173123.232018-5-pbonzini@redhat.com> From: Richard Henderson In-Reply-To: <20220824173123.232018-5-pbonzini@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/24/22 10:31, Paolo Bonzini wrote: > Add generic code generation that takes care of preparing operands > around calls to decode.e.gen in a table-driven manner, so that ALU > operations need not take care of that. > > Signed-off-by: Paolo Bonzini > --- > target/i386/tcg/decode-new.c.inc | 14 +++++++- > target/i386/tcg/emit.c.inc | 62 ++++++++++++++++++++++++++++++++ > 2 files changed, 75 insertions(+), 1 deletion(-) > > diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc > index d661f1f6f0..b53afea9c8 100644 > --- a/target/i386/tcg/decode-new.c.inc > +++ b/target/i386/tcg/decode-new.c.inc > @@ -133,6 +133,7 @@ typedef struct X86DecodedOp { > MemOp ot; /* For b/c/d/p/s/q/v/w/y/z */ > X86ALUOpType alu_op_type; > bool has_ea; > + TCGv v; > } X86DecodedOp; > > struct X86DecodedInsn { > @@ -987,7 +988,18 @@ static target_ulong disas_insn_new(DisasContext *s, CPUState *cpu, int b) > if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) { > gen_load_ea(s, &decode.mem); > } > - decode.e.gen(s, env, &decode); > + if (s->prefix & PREFIX_LOCK) { > + if (decode.op[0].alu_op_type != X86_ALU_MEM) { > + goto illegal_op; > + } > + gen_load(s, s->T1, &decode.op[2], decode.immediate); > + decode.e.gen(s, env, &decode); > + } else { > + gen_load(s, s->T0, &decode.op[1], decode.immediate); > + gen_load(s, s->T1, &decode.op[2], decode.immediate); > + decode.e.gen(s, env, &decode); > + gen_writeback(s, &decode.op[0]); > + } While I can see that you don't want to mix decoding changes with temp lifetime changes... > +static void gen_load(DisasContext *s, TCGv v, X86DecodedOp *op, uint64_t imm) > +{ ... > + op->v = v; > +} Surely this assignment... > +static void gen_writeback(DisasContext *s, X86DecodedOp *op) > +{ ... > + case X86_ALU_GPR: > + gen_op_mov_reg_v(s, op->ot, op->n, s->T0); ... can be used here instead of hard-coding T0. It should be easy enough to create *_v editions of all *_T0, such as gen_movl_seg_T0. r~