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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id c85sm8211907pfc.146.2021.10.29.12.34.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Oct 2021 12:34:43 -0700 (PDT) Subject: Re: [PATCH 3/5] target/riscv: Add a config option for native debug To: Bin Meng , Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20211029152535.2055096-1-bin.meng@windriver.com> <20211029152535.2055096-4-bin.meng@windriver.com> From: Richard Henderson Message-ID: <7bd2521d-756b-9656-cf59-211f7836f883@linaro.org> Date: Fri, 29 Oct 2021 12:34:41 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211029152535.2055096-4-bin.meng@windriver.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.512, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/29/21 8:25 AM, Bin Meng wrote: > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index eface73e7d..3a2fa97098 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -439,6 +439,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > } > > + if (cpu->cfg.debug) { > + set_feature(env, RISCV_FEATURE_DEBUG); > + } > + > set_resetvec(env, cpu->cfg.resetvec); > > /* Validate that MISA_MXL is set properly. */ > @@ -619,6 +623,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), > > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), This half of the patch needs to come as the last patch, after you've finished implementation. The first two hunks might as well fold into the first patch. r~