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Tue, 30 Jan 2024 00:23:56 -0800 (PST) Message-ID: <7bf17208-14ed-48c2-8995-ea4c580f73e2@linaro.org> Date: Tue, 30 Jan 2024 09:23:54 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 32/33] include/exec: Implement cpu_mmu_index generically Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: anjo@rev.ng References: <20240129233043.34558-1-richard.henderson@linaro.org> <20240129233043.34558-33-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240129233043.34558-33-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philmd@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 30/1/24 00:30, Richard Henderson wrote: > For user-only mode, use MMU_USER_IDX. > For system mode, use CPUClass.mmu_index. > > Signed-off-by: Richard Henderson > --- > include/exec/cpu-all.h | 4 ++++ > include/exec/cpu-common.h | 19 +++++++++++++++++++ > target/alpha/cpu.h | 5 ----- > target/arm/cpu.h | 13 ------------- > target/avr/cpu.h | 5 ----- > target/cris/cpu.h | 4 ---- > target/hexagon/cpu.h | 9 --------- > target/hppa/cpu.h | 10 ---------- > target/i386/cpu.h | 6 ------ > target/loongarch/cpu.h | 10 ---------- > target/m68k/cpu.h | 4 ---- > target/microblaze/cpu.h | 6 ------ > target/mips/cpu.h | 5 ----- > target/nios2/cpu.h | 6 ------ > target/openrisc/cpu.h | 6 ------ > target/ppc/cpu.h | 5 ----- > target/riscv/cpu.h | 2 -- > target/rx/cpu.h | 5 ----- > target/s390x/cpu.h | 2 -- > target/sh4/cpu.h | 6 ------ > target/sparc/cpu.h | 6 ------ > target/tricore/cpu.h | 5 ----- > target/xtensa/cpu.h | 5 ----- > target/hppa/cpu.c | 2 +- > target/i386/cpu.c | 2 +- > target/loongarch/cpu.c | 2 +- > target/microblaze/cpu.c | 2 +- > target/nios2/cpu.c | 2 +- > target/openrisc/cpu.c | 2 +- > target/sh4/cpu.c | 2 +- > target/sparc/cpu.c | 2 +- > 31 files changed, 31 insertions(+), 133 deletions(-) > +#ifndef CONFIG_USER_ONLY > +/** > + * cpu_mmu_index: > + * @env: The cpu environment > + * @ifetch: True for code access, false for data access. > + * > + * Return the core mmu index for the current translation regime. > + * This function is used by generic TCG code paths. > + * > + * The user-only version of this function is inline in cpu-all.h, > + * where it always returns MMU_USER_IDX. > + */ > +static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) > +{ > + CPUState *cs = env_cpu(env); > + return cs->cc->mmu_index(cs, ifetch); Can we add here: [tcg_debug_]assert(index < NB_MMU_MODES); > +} > +#endif /* !CONFIG_USER_ONLY */