From: Davidson Francis <davidsondfgl@gmail.com>
To: Richard Henderson <rth@twiddle.net>,
QEMU Development <qemu-devel@nongnu.org>,
Openrisc <openrisc@lists.librecores.org>
Subject: Re: [Qemu-devel] [OpenRISC] OpenRISC: SMP support for more than 2 cores
Date: Fri, 8 Jun 2018 03:48:40 -0300 [thread overview]
Message-ID: <7c9a8e94-2f45-aeba-a12b-0c83c70c6f99@gmail.com> (raw)
In-Reply-To: <5185f351-8f1d-bc81-9806-a5e412cfebb0@twiddle.net>
On 07-06-2018 12:56, Richard Henderson wrote:
> On 06/07/2018 06:27 AM, Davidson Francis wrote:
>> Dear all,
>>
>> Currently Qemu supports only 2 cores when SMP enabled for or1k architecure, so
>> I would like to know if there is a quick way to increase the number of cores by
>> changing a few lines of code or to accomplish this, will requires significant
>> changes in the source code?
>
> Probably not significant changes.
> The limit of 2 seems to be the way the interrupts are wired up.
> That can probably be extended relatively easily.
>
>
> r~
>
Thank you Richard, I will investigate how the interrupts are wired.
Kind regards,
Davidson Francis.
prev parent reply other threads:[~2018-06-08 6:48 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-07 13:27 [Qemu-devel] OpenRISC: SMP support for more than 2 cores Davidson Francis
2018-06-07 15:56 ` [Qemu-devel] [OpenRISC] " Richard Henderson
2018-06-08 6:48 ` Davidson Francis [this message]
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