From: Richard Henderson <richard.henderson@linaro.org>
To: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
"LIU Zhiwei" <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com
Subject: Re: [PATCH v3 20/20] target/riscv: Enable uxl field write
Date: Thu, 11 Nov 2021 19:20:20 +0100 [thread overview]
Message-ID: <7cb12d8b-3439-ad5d-c36f-9b68e4754680@linaro.org> (raw)
In-Reply-To: <00e67460-09de-7b19-3e16-a2f9af3546ae@univ-grenoble-alpes.fr>
On 11/11/21 4:18 PM, Frédéric Pétrot wrote:
>> Still missing the update for write_sstatus, which I think is simply an update to
>> sstatus_v1_10_mask.
>
> I take the liberty to jump in as I face the issue of updating that mask in the
> 128-bit patches: sstatus_v1_10_mask is a target_ulong, and when compiling for
> 32-bit hosts, we can't just or it with MSTATUS64_S/UXL that lie above the
> 32-bit limits.
Surely (target_ulong)MSTATUS64_UXL will properly produce 0 when oring into
sstatus_v1_10_mask? Which is correct for an RV32-only build.
r~
prev parent reply other threads:[~2021-11-11 18:21 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-11 5:57 [PATCH v3 00/20] Support UXL filed in xstatus LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 01/20] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 02/20] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 03/20] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 04/20] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-11 11:19 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 05/20] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 06/20] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2021-11-11 11:21 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 08/20] target/riscv: Create current pm fields in env LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2021-11-11 11:26 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 10/20] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-11 11:28 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2021-11-11 11:29 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 12/20] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-11 11:31 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei
2021-11-11 11:33 ` Richard Henderson
2021-11-11 11:33 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2021-11-11 11:35 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2021-11-11 11:38 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 17/20] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 18/20] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-11 11:46 ` Richard Henderson
2021-11-11 14:43 ` LIU Zhiwei
2021-11-11 5:58 ` [PATCH v3 20/20] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-11 11:49 ` Richard Henderson
2021-11-11 15:18 ` Frédéric Pétrot
2021-11-11 18:20 ` Richard Henderson [this message]
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