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From: Richard Henderson <richard.henderson@linaro.org>
To: Stafford Horne <shorne@gmail.com>
Cc: Openrisc <openrisc@lists.librecores.org>,
	QEMU Development <qemu-devel@nongnu.org>,
	Richard Henderson <rth@twiddle.net>
Subject: Re: [PATCH] target/openrisc: Fix FPCSR mask to allow setting DZF
Date: Thu, 16 Jan 2020 14:51:02 -1000	[thread overview]
Message-ID: <7cbf0cfa-2fa7-ed78-d0b4-5b93d012f265@linaro.org> (raw)
In-Reply-To: <20200110212843.27335-1-shorne@gmail.com>

On 1/10/20 11:28 AM, Stafford Horne wrote:
> The mask used when setting FPCSR allows setting bits 10 to 1.  However,
> OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero
> Flag (DZF).  This seems like an off-by-one bug.
> 
> This was found when testing the GLIBC test suite which has test cases to
> set and clear all bits.
> 
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
>  target/openrisc/fpu_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Thanks, queued.


r~


      reply	other threads:[~2020-01-17  0:51 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-10 21:28 [PATCH] target/openrisc: Fix FPCSR mask to allow setting DZF Stafford Horne
2020-01-17  0:51 ` Richard Henderson [this message]

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