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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c4530b3sm3769913f8f.34.2025.07.31.14.27.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 31 Jul 2025 14:27:42 -0700 (PDT) Message-ID: <7cc71966-5165-430d-80ec-6de6d5e6dc1b@linaro.org> Date: Thu, 31 Jul 2025 23:27:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/3] single-binary: compile hw/intc/arm* files once To: Pierrick Bouvier , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20250725201906.19533-1-pierrick.bouvier@linaro.org> <144f0930-af30-42b0-849c-99242d3f09ee@linaro.org> <25fe9c70-be00-4884-8d91-53dfff745cb6@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <25fe9c70-be00-4884-8d91-53dfff745cb6@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 31/7/25 20:30, Pierrick Bouvier wrote: > On 7/31/25 9:23 AM, Peter Maydell wrote: >> On Mon, 28 Jul 2025 at 20:34, Pierrick Bouvier >> wrote: >>> This old commit (7702e47c2) was the origin of having interrupt related >>> code in a generic folder, but I don't really understand the rationale >>> behind it to be honest. It seems to be an exception regarding all the >>> rest of the codebase, thus the idea to bring back things where they >>> belong. >> >> Most devices are both (a) architecture specific and (b) a particular >> kind of device (UART, ethernet controller, interrupt controller, etc). >> The nature of a filesystem hierarchy is that we can't file them >> in both ways at once. We picked "sort them by kind", which is why >> all the interrupt controllers live in hw/intc, all the UARTS in >> hw/char, ethernet controllers in hw/net, and so on. In this >> breakdown of the world, hw/$ARCH is supposed to be for board models >> and SoC models only. >> >> The GICv3 and the NVIC are odd, because they are very closely >> coupled to the CPU. (A few other interrupt controllers are also >> like this, but many are not: for instance the GICv2 is a distinct >> bit of hardware that communicates with the CPU over the IRQ and >> FIQ lines only.) >> >> One of my post-implementation regrets about GICv3 is that we >> didn't really get the split between the GICv3 proper and its >> CPU interface right. In hardware the GICv3 is an external device >> and the CPU interface is part of the CPU, with a defined >> protocol for talking between them. In QEMU we put all the >> implementation of this in hw/intc/, and the code in arm_gicv3_cpuif.c >> does some ad-hoc installing of hooks into the CPU. >> >> For the GICv5 I'm trying to structure this in a cleaner way that >> is closer to the hardware structure, so the CPU interface >> will be code in target/arm/, with a clearly defined set of >> functions that it calls to talk to the rest of the GIC that >> lives in hw/intc/. (This would be too much upheaval to >> retrofit to GICv3 though, I think.) >> >> In a green-field design of M-profile we might have made >> the NVIC be code in target/arm, and instead of a separate >> device have the CPU object itself do this code. But at the >> time it was written we didn't have the same QOM device >> class setup we did at the time, and IIRC CPU objects >> weren't a subclass of device. > Coming back to our issue, I can see two ways to solve it in a short term: > - On build system: define target hw before generic ones, so we can reuse > all the source sets defined there. This has the advantage to be usable > by all others architectures. That seems the cheaper / quicker way, isn't it? > - Move gic related fields to a substructure in arm cpu, and provide a > simple accessor to it, like "cpu_gicv3(cpu)", breaking the dependency to > cpu.h. Concerned fields would be: gic_num_lrs, gic_vpribits, > gic_vprebits, gic_pribits. FYI a previous attempt to disentangle GIC vs CPU with QOM: https://lore.kernel.org/qemu-devel/20231212162935.42910-1-philmd@linaro.org/