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From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <7cd85d25-3706-e75f-6d29-4a5716d4c516@linaro.org>
Date: Fri, 8 Feb 2019 09:16:50 -0800
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Subject: Re: [Qemu-devel] [PATCH 13/17] target/arm: Set PSTATE.TCO on
 exception entry
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>, qemu-arm <qemu-arm@nongnu.org>

On 2/7/19 9:44 AM, Peter Maydell wrote:
> On Mon, 14 Jan 2019 at 01:12, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> R0085 specifies that exception handlers begin with tag checks overridden.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>  target/arm/helper.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/arm/helper.c b/target/arm/helper.c
>> index df43deb0f8..1e9ccf0b2e 100644
>> --- a/target/arm/helper.c
>> +++ b/target/arm/helper.c
>> @@ -8830,7 +8830,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
>>      qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
>>                    env->elr_el[new_el]);
>>
>> -    pstate_write(env, PSTATE_DAIF | new_mode);
>> +    pstate_write(env, PSTATE_DAIF | PSTATE_TCO | new_mode);
>>      env->aarch64 = 1;
>>      aarch64_restore_sp(env, new_el);
> 
> PSTATE_TCO being set doesn't affect codegen for non-MTE CPUs,
> right?

TCO does not exist before MTE.  I shouldn't set it without MTE, I think, as
it's visible to the guest.

r~