[PATCH 00/18] hw/arm: Move various objects to softmmu_ss to build them once (part 1)

[PATCH 00/18] hw/arm: Move various objects to softmmu_ss to build them once (part 1)

[Philippe Mathieu-Daudé]

Hi,

This series unifies various objects from libqemu-arm-softmmu.fa.p
and libqemu-aarch64-softmmu.fa.p into libcommon.fa.p.

So instead of building each object twice, one for 32-bit ARM ARM
and another for 64-bit Aarch64, hardware-related objects are built
once.

Part #1 is the low hanging fruits :) Also I cut the series under
20 patches to ease review digestion.

The overall logic is to only access ARMCPU as opaque pointer when
possible. This way we don't depend on the (target/arm/) "cpu.h"
header which contains target-specific definitions and forces units
to be added in Meson's arm_ss[] specific source set.

In order to reduce use of "target/arm/cpu.h" by hardware units,
we split the hardware-facing definitions in the new "hw/arm/cpu.h"
header.

Finally, instead of using object_initialize() on the full ARMCPU
variable, we use object_new(TYPE ARM_CPU). Since QOM types are
registered with their class/instance size, we don't need to provide
sizeof(ARMCPU) to allocate the object.

Please review,

Phil.

Based-on: <20230109115316.2235-1-philmd@linaro.org>
          "hw/arm: Cleanups before pflash refactor"

Philippe Mathieu-Daudé (18):
  hw/arm: Move various units to softmmu_ss[]
  hw/arm/boot: Include missing 'exec/cpu-all.h' header
  target/arm/cpregs: Include missing 'target/arm/cpu.h' header
  hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"
  target/arm: Move CPU QOM type definitions to "hw/arm/cpu.h"
  target/arm: Move CPU definitions consumed by HW model to
    "hw/arm/cpu.h"
  hw/arm: Move more units to softmmu_ss[]
  hw/arm: Move units to softmmu[] by replacing "{target ->
    hw}/arm/cpu.h"
  hw/arm/armv7m: Remove 'target/arm/cpu.h' from NVIC header
  hw/arm: Move various armv7m-related units to softmmu_ss[]
  hw/arm/digic: Remove unnecessary target_long use
  hw/arm/digic: Replace object_initialize(ARMCPU) by object_new(ARMCPU)
  hw/arm/fsl-imx: Correct GPIO/GPT index in QOM tree
  hw/arm/fsl-imx25: Replace object_initialize(ARMCPU) by object_new()
  hw/arm/fsl-imx31: Replace object_initialize(ARMCPU) by object_new()
  hw/arm/fsl-imx7: Replace object_initialize(ARMCPU) by object_new()
  hw/arm/fsl-imx6: Replace object_initialize(ARMCPU) by object_new()
  hw/arm/allwinner: Replace object_initialize(ARMCPU) by object_new()

 hw/arm/allwinner-a10.c         | 10 ++--
 hw/arm/allwinner-h3.c          | 14 +++---
 hw/arm/armv7m.c                |  2 +
 hw/arm/boot.c                  |  1 +
 hw/arm/collie.c                |  1 -
 hw/arm/cubieboard.c            |  2 +-
 hw/arm/digic.c                 |  7 +--
 hw/arm/digic_boards.c          |  2 +-
 hw/arm/fsl-imx25.c             |  9 ++--
 hw/arm/fsl-imx31.c             |  9 ++--
 hw/arm/fsl-imx6.c              | 14 +++---
 hw/arm/fsl-imx6ul.c            | 12 ++---
 hw/arm/fsl-imx7.c              | 10 ++--
 hw/arm/gumstix.c               |  1 -
 hw/arm/highbank.c              |  2 +-
 hw/arm/imx25_pdk.c             |  2 +-
 hw/arm/integratorcp.c          |  2 +-
 hw/arm/kzm.c                   |  2 +-
 hw/arm/mainstone.c             |  2 +-
 hw/arm/mcimx6ul-evk.c          |  2 +-
 hw/arm/mcimx7d-sabre.c         |  2 +-
 hw/arm/meson.build             | 83 ++++++++++++++++++----------------
 hw/arm/musicpal.c              |  2 +-
 hw/arm/omap_sx1.c              |  1 -
 hw/arm/palm.c                  |  2 +-
 hw/arm/sabrelite.c             |  2 +-
 hw/arm/spitz.c                 |  2 +-
 hw/arm/strongarm.c             |  2 +-
 hw/arm/z2.c                    |  1 -
 include/hw/arm/allwinner-a10.h |  4 +-
 include/hw/arm/allwinner-h3.h  |  4 +-
 include/hw/arm/cpu.h           | 77 +++++++++++++++++++++++++++++++
 include/hw/arm/digic.h         |  4 +-
 include/hw/arm/fsl-imx25.h     |  4 +-
 include/hw/arm/fsl-imx31.h     |  4 +-
 include/hw/arm/fsl-imx6.h      |  4 +-
 include/hw/arm/fsl-imx6ul.h    |  4 +-
 include/hw/arm/fsl-imx7.h      |  4 +-
 include/hw/intc/armv7m_nvic.h  |  2 +-
 target/arm/cpregs.h            |  2 +
 target/arm/cpu-qom.h           | 28 +-----------
 target/arm/cpu.h               | 42 ++---------------
 42 files changed, 205 insertions(+), 181 deletions(-)
 create mode 100644 include/hw/arm/cpu.h

-- 
2.38.1

[PATCH 01/18] hw/arm: Move various units to softmmu_ss[]

[Philippe Mathieu-Daudé]

arm_ss[] units are built twice: once for 32-bit word size and
once for 64-bit. The following units don't require any word
size knowledge and can be moved to softmmu_ss[] (where they
are built once):

 - smmu-common.c
 - exynos4_boards.c
 - bcm2835_peripherals.c
 - tosa.c

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/meson.build | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 92f9f6e000..4babaa8dfc 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -3,7 +3,6 @@ arm_ss.add(files('boot.c'), fdt)
 arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
 arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
 arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
-arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
 arm_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
 arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
 arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
@@ -18,7 +17,6 @@ arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
 arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
 arm_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
 arm_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c'))
-arm_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c'))
 arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
 arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
 arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
@@ -38,7 +36,7 @@ arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c'))
 arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
-arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c'))
+arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
 arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
 arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
 arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
@@ -59,8 +57,13 @@ arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
 arm_ss.add(when: 'CONFIG_MUSCA', if_true: files('musca.c'))
 arm_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c'))
 arm_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c'))
-arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c', 'smmuv3.c'))
+arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))
 arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c'))
 arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c'))
 
+softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c'))
+softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
+softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c'))
+softmmu_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c'))
+
 hw_arch += {'arm': arm_ss}
-- 
2.38.1

Re: [PATCH 01/18] hw/arm: Move various units to softmmu_ss[]

[Richard Henderson]

On 1/10/23 08:43, Philippe Mathieu-Daudé wrote:
> arm_ss[] units are built twice: once for 32-bit word size and
> once for 64-bit. The following units don't require any word
> size knowledge and can be moved to softmmu_ss[] (where they
> are built once):
> 
>   - smmu-common.c
>   - exynos4_boards.c
>   - bcm2835_peripherals.c
>   - tosa.c
> 
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
>   hw/arm/meson.build | 11 +++++++----
>   1 file changed, 7 insertions(+), 4 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[PATCH 02/18] hw/arm/boot: Include missing 'exec/cpu-all.h' header

[Philippe Mathieu-Daudé]

default_reset_secondary() uses address_space_stl_notdirty(),
itself declared in "exec/cpu-all.h". Include this header in
order to avoid when refactoring headers:

  ../hw/arm/boot.c:281:5: error: implicit declaration of function 'address_space_stl_notdirty' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
    address_space_stl_notdirty(as, info->smp_bootreg_addr,
    ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/boot.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 3d7d11f782..f5bfb922b1 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -25,6 +25,7 @@
 #include "qemu/config-file.h"
 #include "qemu/option.h"
 #include "qemu/units.h"
+#include "exec/cpu-all.h"
 
 /* Kernel boot protocol is specified in the kernel docs
  * Documentation/arm/Booting and Documentation/arm64/booting.txt
-- 
2.38.1

Re: [PATCH 02/18] hw/arm/boot: Include missing 'exec/cpu-all.h' header

[Richard Henderson]

On 1/10/23 08:43, Philippe Mathieu-Daudé wrote:
> default_reset_secondary() uses address_space_stl_notdirty(),
> itself declared in "exec/cpu-all.h". Include this header in
> order to avoid when refactoring headers:
> 
>    ../hw/arm/boot.c:281:5: error: implicit declaration of function 'address_space_stl_notdirty' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
>      address_space_stl_notdirty(as, info->smp_bootreg_addr,
>      ^
> 
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
>   hw/arm/boot.c | 1 +
>   1 file changed, 1 insertion(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH 03/18] target/arm/cpregs: Include missing 'target/arm/cpu.h' header

[Philippe Mathieu-Daudé]

CPReadFn type definitions use the CPUARMState type, itself
declared in "target/arm/cpu.h". Include this file in order
to avoid when refactoring headers:

  ../target/arm/cpregs.h:241:27: error: unknown type name 'CPUARMState'
  typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
                            ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/cpregs.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 7e78c2c05c..63b645907e 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -21,6 +21,8 @@
 #ifndef TARGET_ARM_CPREGS_H
 #define TARGET_ARM_CPREGS_H
 
+#include "target/arm/cpu.h"
+
 /*
  * ARMCPRegInfo type field bits:
  */
-- 
2.38.1

Re: [PATCH 03/18] target/arm/cpregs: Include missing 'target/arm/cpu.h' header

[Richard Henderson]

On 1/10/23 08:43, Philippe Mathieu-Daudé wrote:
> +#include "target/arm/cpu.h"

Just "cpu.h" in this file.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH 04/18] hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"

[Philippe Mathieu-Daudé]

First we want to introduce a new "cpu.h" header in the "hw/arm/"
namespace; second we would like to get rid of '-I target/$ARCH/'
in the CPPFLAGS.
Use the full path to "cpu.h": "target/arm/cpu.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/arm/digic.h      | 2 +-
 include/hw/arm/fsl-imx6.h   | 2 +-
 include/hw/arm/fsl-imx6ul.h | 2 +-
 include/hw/arm/fsl-imx7.h   | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/hw/arm/digic.h b/include/hw/arm/digic.h
index 8f2735c284..646802806e 100644
--- a/include/hw/arm/digic.h
+++ b/include/hw/arm/digic.h
@@ -18,7 +18,7 @@
 #ifndef HW_ARM_DIGIC_H
 #define HW_ARM_DIGIC_H
 
-#include "cpu.h"
+#include "target/arm/cpu.h"
 #include "hw/timer/digic-timer.h"
 #include "hw/char/digic-uart.h"
 #include "qom/object.h"
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index 83291457cf..9d24d98189 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -33,7 +33,7 @@
 #include "hw/usb/chipidea.h"
 #include "hw/usb/imx-usb-phy.h"
 #include "exec/memory.h"
-#include "cpu.h"
+#include "target/arm/cpu.h"
 #include "qom/object.h"
 
 #define TYPE_FSL_IMX6 "fsl-imx6"
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index 7812e516a5..4f42fe4192 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -37,7 +37,7 @@
 #include "hw/usb/chipidea.h"
 #include "hw/usb/imx-usb-phy.h"
 #include "exec/memory.h"
-#include "cpu.h"
+#include "target/arm/cpu.h"
 #include "qom/object.h"
 
 #define TYPE_FSL_IMX6UL "fsl-imx6ul"
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index 4e5e071864..ed8c1ec813 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -38,7 +38,7 @@
 #include "hw/net/imx_fec.h"
 #include "hw/pci-host/designware.h"
 #include "hw/usb/chipidea.h"
-#include "cpu.h"
+#include "target/arm/cpu.h"
 #include "qom/object.h"
 
 #define TYPE_FSL_IMX7 "fsl-imx7"
-- 
2.38.1

Re: [PATCH 04/18] hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"

[Richard Henderson]

On 1/10/23 08:43, Philippe Mathieu-Daudé wrote:
> First we want to introduce a new "cpu.h" header in the "hw/arm/"
> namespace;

Do we?  Is that really the best name (not having seen its contents).

> second we would like to get rid of '-I target/$ARCH/'
> in the CPPFLAGS.
> Use the full path to "cpu.h": "target/arm/cpu.h".

That seems a worthy goal for hw/ though.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[PATCH 05/18] target/arm: Move CPU QOM type definitions to "hw/arm/cpu.h"

[Philippe Mathieu-Daudé]

Units including "target/arm/cpu.h" can't be built once via meson's
softmmu_ss[] source set. Since this header depends on specific
definitions such the word size (32 or 64-bit), for ARM such units
must go to the per-target arm_ss[].

We want to expose few architectural definitions to hardware models.

Start by exposing the ARM CPU QOM types to files under hw/
via the new "hw/arm/cpu.h" header. Doing so, less HW models
will require access to "target/arm/cpu.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/arm/cpu.h | 28 ++++++++++++++++++++++++++++
 target/arm/cpu-qom.h | 13 +------------
 target/arm/cpu.h     |  8 ++++----
 3 files changed, 33 insertions(+), 16 deletions(-)
 create mode 100644 include/hw/arm/cpu.h

diff --git a/include/hw/arm/cpu.h b/include/hw/arm/cpu.h
new file mode 100644
index 0000000000..0c5d6ca2a8
--- /dev/null
+++ b/include/hw/arm/cpu.h
@@ -0,0 +1,28 @@
+/*
+ * ARM / Aarch64 CPU definitions
+ *
+ * This file contains architectural definitions consumed by hardware models
+ * implementations (files under hw/).
+ * Definitions not required to be exposed to hardware has to go in the
+ * architecture specific "target/arm/cpu.h" header.
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#ifndef HW_ARM_CPU_H
+#define HW_ARM_CPU_H
+
+#include "hw/core/cpu.h"
+
+#define TYPE_ARM_CPU "arm-cpu"
+OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
+
+#define TYPE_AARCH64_CPU "aarch64-cpu"
+typedef struct AArch64CPUClass AArch64CPUClass;
+DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU)
+
+#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
+#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
+
+#endif
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index 514c22ced9..b98904b6bc 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -21,16 +21,11 @@
 #define QEMU_ARM_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "hw/arm/cpu.h"
 #include "qom/object.h"
 
 struct arm_boot_info;
 
-#define TYPE_ARM_CPU "arm-cpu"
-
-OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
-
-#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
-
 typedef struct ARMCPUInfo {
     const char *name;
     void (*initfn)(Object *obj);
@@ -57,12 +52,6 @@ struct ARMCPUClass {
     ResettablePhases parent_phases;
 };
 
-
-#define TYPE_AARCH64_CPU "aarch64-cpu"
-typedef struct AArch64CPUClass AArch64CPUClass;
-DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
-                       TYPE_AARCH64_CPU)
-
 struct AArch64CPUClass {
     /*< private >*/
     ARMCPUClass parent_class;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index bf2bce046d..52ac99cad3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -17,8 +17,8 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef ARM_CPU_H
-#define ARM_CPU_H
+#ifndef TARGET_ARM_CPU_H
+#define TARGET_ARM_CPU_H
 
 #include "kvm-consts.h"
 #include "qemu/cpu-float.h"
@@ -26,6 +26,7 @@
 #include "cpu-qom.h"
 #include "exec/cpu-defs.h"
 #include "qapi/qapi-types-common.h"
+#include "hw/arm/cpu.h"
 
 /* ARM processors have a weak memory model */
 #define TCG_GUEST_DEFAULT_MO      (0)
@@ -2853,11 +2854,10 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
 #define ARM_CPUID_TI915T      0x54029152
 #define ARM_CPUID_TI925T      0x54029252
 
-#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
-#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
 
 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
+#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
 
 #define cpu_list arm_cpu_list
 
-- 
2.38.1

Re: [PATCH 05/18] target/arm: Move CPU QOM type definitions to "hw/arm/cpu.h"

[Richard Henderson]

On 1/10/23 08:43, Philippe Mathieu-Daudé wrote:
> +++ b/target/arm/cpu.h
> @@ -26,6 +26,7 @@
>   #include "cpu-qom.h"
>   #include "exec/cpu-defs.h"
>   #include "qapi/qapi-types-common.h"
> +#include "hw/arm/cpu.h"

I'm not a fan of this.

If you want a smaller version of cpu-qom.h here in target/arm/, for use by hw/, that's one 
thing.  But target/ should not be reaching back into hw/, IMO.


r~

Re: [PATCH 05/18] target/arm: Move CPU QOM type definitions to "hw/arm/cpu.h"

[Philippe Mathieu-Daudé]

On 11/1/23 21:02, Richard Henderson wrote:
> On 1/10/23 08:43, Philippe Mathieu-Daudé wrote:
>> +++ b/target/arm/cpu.h
>> @@ -26,6 +26,7 @@
>>   #include "cpu-qom.h"
>>   #include "exec/cpu-defs.h"
>>   #include "qapi/qapi-types-common.h"
>> +#include "hw/arm/cpu.h"
> 
> I'm not a fan of this.
> 
> If you want a smaller version of cpu-qom.h here in target/arm/, for use 
> by hw/, that's one thing.  But target/ should not be reaching back into 
> hw/, IMO.

I concur, but currently we have:

$ git grep '#include "hw' target | wc -l
      220

$ git grep -h '#include "hw' target | sort | uniq -c
    1 #include "hw/acpi/acpi.h"
    1 #include "hw/acpi/ghes.h"
    1 #include "hw/arm/boot.h"
    1 #include "hw/arm/virt.h"
   19 #include "hw/boards.h"
    2 #include "hw/clock.h"
    3 #include "hw/core/accel-cpu.h"
   24 #include "hw/core/cpu.h"
   20 #include "hw/core/sysemu-cpu-ops.h"
   24 #include "hw/core/tcg-cpu-ops.h"
    1 #include "hw/hppa/hppa_hardware.h"
    3 #include "hw/hw.h"
    1 #include "hw/hyperv/hyperv-proto.h"
    2 #include "hw/hyperv/hyperv.h"
    2 #include "hw/i386/apic-msidef.h"
    2 #include "hw/i386/apic.h"
    8 #include "hw/i386/apic_internal.h"
    1 #include "hw/i386/e820_memory_layout.h"
    1 #include "hw/i386/intel_iommu.h"
    1 #include "hw/i386/ioapic.h"
    2 #include "hw/i386/pc.h"
    1 #include "hw/i386/sgx-epc.h"
    1 #include "hw/i386/topology.h"
    1 #include "hw/i386/x86-iommu.h"
    2 #include "hw/i386/x86.h"
    1 #include "hw/intc/riscv_aclint.h"
    8 #include "hw/irq.h"
    1 #include "hw/isa/isa.h"
    5 #include "hw/loader.h"
    1 #include "hw/loongarch/virt.h"
    2 #include "hw/mips/cpudevs.h"
    2 #include "hw/pci/msi.h"
    1 #include "hw/pci/msix.h"
    3 #include "hw/pci/pci.h"
    1 #include "hw/ppc/openpic_kvm.h"
    5 #include "hw/ppc/ppc.h"
    2 #include "hw/ppc/spapr.h"
    1 #include "hw/ppc/spapr_cpu_core.h"
    2 #include "hw/qdev-clock.h"
   12 #include "hw/qdev-properties.h"
   11 #include "hw/registerfields.h"
    2 #include "hw/s390x/ebcdic.h"
    5 #include "hw/s390x/ioinst.h"
    2 #include "hw/s390x/ipl.h"
    8 #include "hw/s390x/pv.h"
    2 #include "hw/s390x/s390-pci-bus.h"
    2 #include "hw/s390x/s390-pci-inst.h"
    2 #include "hw/s390x/s390-virtio-ccw.h"
    2 #include "hw/s390x/s390-virtio-hcall.h"
    3 #include "hw/s390x/s390_flic.h"
    1 #include "hw/s390x/sclp.h"
    2 #include "hw/s390x/storage-keys.h"
    1 #include "hw/s390x/tod.h"
    1 #include "hw/sh4/sh_intc.h"
    2 #include "hw/sysbus.h"
    1 #include "hw/watchdog/wdt_diag288.h"
    1 #include "hw/xtensa/xtensa-isa.h"

Assuming we want to have a self-contained libtarget$arch, how can we
deal with HW tied to the arch such CPU timers or NVIC?

Re: [PATCH 05/18] target/arm: Move CPU QOM type definitions to "hw/arm/cpu.h"

[Philippe Mathieu-Daudé]

Cc'ing Pierrick

On 12/1/23 08:17, Philippe Mathieu-Daudé wrote:
> On 11/1/23 21:02, Richard Henderson wrote:
>> On 1/10/23 08:43, Philippe Mathieu-Daudé wrote:
>>> +++ b/target/arm/cpu.h
>>> @@ -26,6 +26,7 @@
>>>   #include "cpu-qom.h"
>>>   #include "exec/cpu-defs.h"
>>>   #include "qapi/qapi-types-common.h"
>>> +#include "hw/arm/cpu.h"
>>
>> I'm not a fan of this.
>>
>> If you want a smaller version of cpu-qom.h here in target/arm/, for 
>> use by hw/, that's one thing.  But target/ should not be reaching back 
>> into hw/, IMO.
> 
> I concur, but currently we have:
> 
> $ git grep '#include "hw' target | wc -l
>       220
> 
> $ git grep -h '#include "hw' target | sort | uniq -c
>     1 #include "hw/acpi/acpi.h"
>     1 #include "hw/acpi/ghes.h"
>     1 #include "hw/arm/boot.h"
>     1 #include "hw/arm/virt.h"
>    19 #include "hw/boards.h"
>     2 #include "hw/clock.h"
>     3 #include "hw/core/accel-cpu.h"
>    24 #include "hw/core/cpu.h"
>    20 #include "hw/core/sysemu-cpu-ops.h"
>    24 #include "hw/core/tcg-cpu-ops.h"
>     1 #include "hw/hppa/hppa_hardware.h"
>     3 #include "hw/hw.h"
>     1 #include "hw/hyperv/hyperv-proto.h"
>     2 #include "hw/hyperv/hyperv.h"
>     2 #include "hw/i386/apic-msidef.h"
>     2 #include "hw/i386/apic.h"
>     8 #include "hw/i386/apic_internal.h"
>     1 #include "hw/i386/e820_memory_layout.h"
>     1 #include "hw/i386/intel_iommu.h"
>     1 #include "hw/i386/ioapic.h"
>     2 #include "hw/i386/pc.h"
>     1 #include "hw/i386/sgx-epc.h"
>     1 #include "hw/i386/topology.h"
>     1 #include "hw/i386/x86-iommu.h"
>     2 #include "hw/i386/x86.h"
>     1 #include "hw/intc/riscv_aclint.h"
>     8 #include "hw/irq.h"
>     1 #include "hw/isa/isa.h"
>     5 #include "hw/loader.h"
>     1 #include "hw/loongarch/virt.h"
>     2 #include "hw/mips/cpudevs.h"
>     2 #include "hw/pci/msi.h"
>     1 #include "hw/pci/msix.h"
>     3 #include "hw/pci/pci.h"
>     1 #include "hw/ppc/openpic_kvm.h"
>     5 #include "hw/ppc/ppc.h"
>     2 #include "hw/ppc/spapr.h"
>     1 #include "hw/ppc/spapr_cpu_core.h"
>     2 #include "hw/qdev-clock.h"
>    12 #include "hw/qdev-properties.h"
>    11 #include "hw/registerfields.h"
>     2 #include "hw/s390x/ebcdic.h"
>     5 #include "hw/s390x/ioinst.h"
>     2 #include "hw/s390x/ipl.h"
>     8 #include "hw/s390x/pv.h"
>     2 #include "hw/s390x/s390-pci-bus.h"
>     2 #include "hw/s390x/s390-pci-inst.h"
>     2 #include "hw/s390x/s390-virtio-ccw.h"
>     2 #include "hw/s390x/s390-virtio-hcall.h"
>     3 #include "hw/s390x/s390_flic.h"
>     1 #include "hw/s390x/sclp.h"
>     2 #include "hw/s390x/storage-keys.h"
>     1 #include "hw/s390x/tod.h"
>     1 #include "hw/sh4/sh_intc.h"
>     2 #include "hw/sysbus.h"
>     1 #include "hw/watchdog/wdt_diag288.h"
>     1 #include "hw/xtensa/xtensa-isa.h"
> 
> Assuming we want to have a self-contained libtarget$arch, how can we
> deal with HW tied to the arch such CPU timers or NVIC?

Re: [PATCH 05/18] target/arm: Move CPU QOM type definitions to "hw/arm/cpu.h"

[Philippe Mathieu-Daudé]

On 2/4/25 06:06, Philippe Mathieu-Daudé wrote:
> Cc'ing Pierrick
> 
> On 12/1/23 08:17, Philippe Mathieu-Daudé wrote:
>> On 11/1/23 21:02, Richard Henderson wrote:
>>> On 1/10/23 08:43, Philippe Mathieu-Daudé wrote:
>>>> +++ b/target/arm/cpu.h
>>>> @@ -26,6 +26,7 @@
>>>>   #include "cpu-qom.h"
>>>>   #include "exec/cpu-defs.h"
>>>>   #include "qapi/qapi-types-common.h"
>>>> +#include "hw/arm/cpu.h"
>>>
>>> I'm not a fan of this.
>>>
>>> If you want a smaller version of cpu-qom.h here in target/arm/, for 
>>> use by hw/, that's one thing.  But target/ should not be reaching 
>>> back into hw/, IMO.

Giving it more thought, we should keep "target/foo/cpu.h" private to
target/foo/, and only access its fields from hw/ via clearly defined
methods/constants.

>>
>> I concur, but currently we have:
>>
>> $ git grep '#include "hw' target | wc -l
>>       220
>>
>> $ git grep -h '#include "hw' target | sort | uniq -c
>>     1 #include "hw/acpi/acpi.h"
>>     1 #include "hw/acpi/ghes.h"
>>     1 #include "hw/arm/boot.h"
>>     1 #include "hw/arm/virt.h"
>>    19 #include "hw/boards.h"
>>     2 #include "hw/clock.h"
>>     3 #include "hw/core/accel-cpu.h"
>>    24 #include "hw/core/cpu.h"
>>    20 #include "hw/core/sysemu-cpu-ops.h"
>>    24 #include "hw/core/tcg-cpu-ops.h"
>>     1 #include "hw/hppa/hppa_hardware.h"
>>     3 #include "hw/hw.h"
>>     1 #include "hw/hyperv/hyperv-proto.h"
>>     2 #include "hw/hyperv/hyperv.h"
>>     2 #include "hw/i386/apic-msidef.h"
>>     2 #include "hw/i386/apic.h"
>>     8 #include "hw/i386/apic_internal.h"
>>     1 #include "hw/i386/e820_memory_layout.h"
>>     1 #include "hw/i386/intel_iommu.h"
>>     1 #include "hw/i386/ioapic.h"
>>     2 #include "hw/i386/pc.h"
>>     1 #include "hw/i386/sgx-epc.h"
>>     1 #include "hw/i386/topology.h"
>>     1 #include "hw/i386/x86-iommu.h"
>>     2 #include "hw/i386/x86.h"
>>     1 #include "hw/intc/riscv_aclint.h"
>>     8 #include "hw/irq.h"
>>     1 #include "hw/isa/isa.h"
>>     5 #include "hw/loader.h"
>>     1 #include "hw/loongarch/virt.h"
>>     2 #include "hw/mips/cpudevs.h"
>>     2 #include "hw/pci/msi.h"
>>     1 #include "hw/pci/msix.h"
>>     3 #include "hw/pci/pci.h"
>>     1 #include "hw/ppc/openpic_kvm.h"
>>     5 #include "hw/ppc/ppc.h"
>>     2 #include "hw/ppc/spapr.h"
>>     1 #include "hw/ppc/spapr_cpu_core.h"
>>     2 #include "hw/qdev-clock.h"
>>    12 #include "hw/qdev-properties.h"
>>    11 #include "hw/registerfields.h"
>>     2 #include "hw/s390x/ebcdic.h"
>>     5 #include "hw/s390x/ioinst.h"
>>     2 #include "hw/s390x/ipl.h"
>>     8 #include "hw/s390x/pv.h"
>>     2 #include "hw/s390x/s390-pci-bus.h"
>>     2 #include "hw/s390x/s390-pci-inst.h"
>>     2 #include "hw/s390x/s390-virtio-ccw.h"
>>     2 #include "hw/s390x/s390-virtio-hcall.h"
>>     3 #include "hw/s390x/s390_flic.h"
>>     1 #include "hw/s390x/sclp.h"
>>     2 #include "hw/s390x/storage-keys.h"
>>     1 #include "hw/s390x/tod.h"
>>     1 #include "hw/sh4/sh_intc.h"
>>     2 #include "hw/sysbus.h"
>>     1 #include "hw/watchdog/wdt_diag288.h"
>>     1 #include "hw/xtensa/xtensa-isa.h"
>>
>> Assuming we want to have a self-contained libtarget$arch, how can we
>> deal with HW tied to the arch such CPU timers or NVIC?
> 

Re: [PATCH 05/18] target/arm: Move CPU QOM type definitions to "hw/arm/cpu.h"

[Pierrick Bouvier]

On 4/1/25 21:06, Philippe Mathieu-Daudé wrote:
> Cc'ing Pierrick
> 
> On 12/1/23 08:17, Philippe Mathieu-Daudé wrote:
>> On 11/1/23 21:02, Richard Henderson wrote:
>>> On 1/10/23 08:43, Philippe Mathieu-Daudé wrote:
>>>> +++ b/target/arm/cpu.h
>>>> @@ -26,6 +26,7 @@
>>>>    #include "cpu-qom.h"
>>>>    #include "exec/cpu-defs.h"
>>>>    #include "qapi/qapi-types-common.h"
>>>> +#include "hw/arm/cpu.h"
>>>
>>> I'm not a fan of this.
>>>
>>> If you want a smaller version of cpu-qom.h here in target/arm/, for
>>> use by hw/, that's one thing.  But target/ should not be reaching back
>>> into hw/, IMO.
>>
>> I concur, but currently we have:
>>
>> $ git grep '#include "hw' target | wc -l
>>        220
>>
>> $ git grep -h '#include "hw' target | sort | uniq -c
>>      1 #include "hw/acpi/acpi.h"
>>      1 #include "hw/acpi/ghes.h"
>>      1 #include "hw/arm/boot.h"
>>      1 #include "hw/arm/virt.h"
>>     19 #include "hw/boards.h"
>>      2 #include "hw/clock.h"
>>      3 #include "hw/core/accel-cpu.h"
>>     24 #include "hw/core/cpu.h"
>>     20 #include "hw/core/sysemu-cpu-ops.h"
>>     24 #include "hw/core/tcg-cpu-ops.h"
>>      1 #include "hw/hppa/hppa_hardware.h"
>>      3 #include "hw/hw.h"
>>      1 #include "hw/hyperv/hyperv-proto.h"
>>      2 #include "hw/hyperv/hyperv.h"
>>      2 #include "hw/i386/apic-msidef.h"
>>      2 #include "hw/i386/apic.h"
>>      8 #include "hw/i386/apic_internal.h"
>>      1 #include "hw/i386/e820_memory_layout.h"
>>      1 #include "hw/i386/intel_iommu.h"
>>      1 #include "hw/i386/ioapic.h"
>>      2 #include "hw/i386/pc.h"
>>      1 #include "hw/i386/sgx-epc.h"
>>      1 #include "hw/i386/topology.h"
>>      1 #include "hw/i386/x86-iommu.h"
>>      2 #include "hw/i386/x86.h"
>>      1 #include "hw/intc/riscv_aclint.h"
>>      8 #include "hw/irq.h"
>>      1 #include "hw/isa/isa.h"
>>      5 #include "hw/loader.h"
>>      1 #include "hw/loongarch/virt.h"
>>      2 #include "hw/mips/cpudevs.h"
>>      2 #include "hw/pci/msi.h"
>>      1 #include "hw/pci/msix.h"
>>      3 #include "hw/pci/pci.h"
>>      1 #include "hw/ppc/openpic_kvm.h"
>>      5 #include "hw/ppc/ppc.h"
>>      2 #include "hw/ppc/spapr.h"
>>      1 #include "hw/ppc/spapr_cpu_core.h"
>>      2 #include "hw/qdev-clock.h"
>>     12 #include "hw/qdev-properties.h"
>>     11 #include "hw/registerfields.h"
>>      2 #include "hw/s390x/ebcdic.h"
>>      5 #include "hw/s390x/ioinst.h"
>>      2 #include "hw/s390x/ipl.h"
>>      8 #include "hw/s390x/pv.h"
>>      2 #include "hw/s390x/s390-pci-bus.h"
>>      2 #include "hw/s390x/s390-pci-inst.h"
>>      2 #include "hw/s390x/s390-virtio-ccw.h"
>>      2 #include "hw/s390x/s390-virtio-hcall.h"
>>      3 #include "hw/s390x/s390_flic.h"
>>      1 #include "hw/s390x/sclp.h"
>>      2 #include "hw/s390x/storage-keys.h"
>>      1 #include "hw/s390x/tod.h"
>>      1 #include "hw/sh4/sh_intc.h"
>>      2 #include "hw/sysbus.h"
>>      1 #include "hw/watchdog/wdt_diag288.h"
>>      1 #include "hw/xtensa/xtensa-isa.h"
>>
>> Assuming we want to have a self-contained libtarget$arch, how can we
>> deal with HW tied to the arch such CPU timers or NVIC?

It's not what we'll achieve.
Right now, what we call libX in meson.build is simply a selection of 
object files, without any guarantee that they don't have external 
dependency on symbols from other libraries. We use that to apply 
specific compilation flags to a set of files, and this is what we really 
achieve here.

Yes, ideally, it would be better if hw was a leaf library in our 
dependency graph.
However, it's not needed to solve this now, and it's not unblocking 
anything to be able to build a single binary, so I don't see it as a 
priority.

> 

[PATCH 06/18] target/arm: Move CPU definitions consumed by HW model to "hw/arm/cpu.h"

[Philippe Mathieu-Daudé]

Units including "target/arm/cpu.h" can't be built once via meson's
softmmu_ss[] source set. Since this header depends on specific
definitions such the word size (32 or 64-bit), for ARM such units
must go to the per-target arm_ss[].

We want to expose few architectural definitions to hardware models.

Expose the ARM architectural definitions used by hardware models,
in order to reduce the inclusion of "target/arm/cpu.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/arm/cpu.h | 49 ++++++++++++++++++++++++++++++++++++++++++++
 target/arm/cpu-qom.h | 15 --------------
 target/arm/cpu.h     | 34 ------------------------------
 3 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/include/hw/arm/cpu.h b/include/hw/arm/cpu.h
index 0c5d6ca2a8..6758bffe34 100644
--- a/include/hw/arm/cpu.h
+++ b/include/hw/arm/cpu.h
@@ -25,4 +25,53 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU)
 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
 
+enum QemuPsciConduit {
+    QEMU_PSCI_CONDUIT_DISABLED = 0,
+    QEMU_PSCI_CONDUIT_SMC = 1,
+    QEMU_PSCI_CONDUIT_HVC = 2,
+};
+
+/* Meanings of the ARMCPU object's four inbound GPIO lines */
+#define ARM_CPU_IRQ 0
+#define ARM_CPU_FIQ 1
+#define ARM_CPU_VIRQ 2
+#define ARM_CPU_VFIQ 3
+
+#define GTIMER_PHYS     0
+#define GTIMER_VIRT     1
+#define GTIMER_HYP      2
+#define GTIMER_SEC      3
+#define GTIMER_HYPVIRT  4
+#define NUM_GTIMERS     5
+
+/* For M profile, some registers are banked secure vs non-secure;
+ * these are represented as a 2-element array where the first element
+ * is the non-secure copy and the second is the secure copy.
+ * When the CPU does not have implement the security extension then
+ * only the first element is used.
+ * This means that the copy for the current security state can be
+ * accessed via env->registerfield[env->v7m.secure] (whether the security
+ * extension is implemented or not).
+ */
+enum {
+    M_REG_NS = 0,
+    M_REG_S = 1,
+    M_REG_NUM_BANKS = 2,
+};
+
+#define ARM_AFF0_SHIFT 0
+#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
+#define ARM_AFF1_SHIFT 8
+#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
+#define ARM_AFF2_SHIFT 16
+#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
+#define ARM_AFF3_SHIFT 32
+#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
+#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
+
+#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
+#define ARM64_AFFINITY_MASK \
+    (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
+#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
+
 #endif
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index b98904b6bc..d37037e214 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -68,19 +68,4 @@ void arm_gt_htimer_cb(void *opaque);
 void arm_gt_stimer_cb(void *opaque);
 void arm_gt_hvtimer_cb(void *opaque);
 
-#define ARM_AFF0_SHIFT 0
-#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
-#define ARM_AFF1_SHIFT 8
-#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
-#define ARM_AFF2_SHIFT 16
-#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
-#define ARM_AFF3_SHIFT 32
-#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
-#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
-
-#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
-#define ARM64_AFFINITY_MASK \
-    (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
-#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
-
 #endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 52ac99cad3..ab6fdecf48 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -72,21 +72,6 @@
 #define ARMV7M_EXCP_PENDSV  14
 #define ARMV7M_EXCP_SYSTICK 15
 
-/* For M profile, some registers are banked secure vs non-secure;
- * these are represented as a 2-element array where the first element
- * is the non-secure copy and the second is the secure copy.
- * When the CPU does not have implement the security extension then
- * only the first element is used.
- * This means that the copy for the current security state can be
- * accessed via env->registerfield[env->v7m.secure] (whether the security
- * extension is implemented or not).
- */
-enum {
-    M_REG_NS = 0,
-    M_REG_S = 1,
-    M_REG_NUM_BANKS = 2,
-};
-
 /* ARM-specific interrupt pending bits.  */
 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
 #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
@@ -107,12 +92,6 @@ enum {
 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
 #endif
 
-/* Meanings of the ARMCPU object's four inbound GPIO lines */
-#define ARM_CPU_IRQ 0
-#define ARM_CPU_FIQ 1
-#define ARM_CPU_VIRQ 2
-#define ARM_CPU_VFIQ 3
-
 /* ARM-specific extra insn start words:
  * 1: Conditional execution bits
  * 2: Partial exception syndrome for data aborts
@@ -160,13 +139,6 @@ typedef struct ARMGenericTimer {
     uint64_t ctl; /* Timer Control register */
 } ARMGenericTimer;
 
-#define GTIMER_PHYS     0
-#define GTIMER_VIRT     1
-#define GTIMER_HYP      2
-#define GTIMER_SEC      3
-#define GTIMER_HYPVIRT  4
-#define NUM_GTIMERS     5
-
 #define VTCR_NSW (1u << 29)
 #define VTCR_NSA (1u << 30)
 #define VSTCR_SW VTCR_NSW
@@ -3323,12 +3295,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env)
 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
                           target_ulong *cs_base, uint32_t *flags);
 
-enum {
-    QEMU_PSCI_CONDUIT_DISABLED = 0,
-    QEMU_PSCI_CONDUIT_SMC = 1,
-    QEMU_PSCI_CONDUIT_HVC = 2,
-};
-
 #ifndef CONFIG_USER_ONLY
 /* Return the address space index to use for a memory access */
 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
-- 
2.38.1

Re: [PATCH 06/18] target/arm: Move CPU definitions consumed by HW model to "hw/arm/cpu.h"

[Philippe Mathieu-Daudé]

Cc'ing Pierrick

On 10/1/23 17:43, Philippe Mathieu-Daudé wrote:
> Units including "target/arm/cpu.h" can't be built once via meson's
> softmmu_ss[] source set. Since this header depends on specific
> definitions such the word size (32 or 64-bit), for ARM such units
> must go to the per-target arm_ss[].
> 
> We want to expose few architectural definitions to hardware models.
> 
> Expose the ARM architectural definitions used by hardware models,
> in order to reduce the inclusion of "target/arm/cpu.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   include/hw/arm/cpu.h | 49 ++++++++++++++++++++++++++++++++++++++++++++

Richard, WRT your comment in previous patch (target/ shouldn't access
hw/), WDYT of "target/arm/hw-defs.h" for this header?

>   target/arm/cpu-qom.h | 15 --------------
>   target/arm/cpu.h     | 34 ------------------------------
>   3 files changed, 49 insertions(+), 49 deletions(-)
> 
> diff --git a/include/hw/arm/cpu.h b/include/hw/arm/cpu.h
> index 0c5d6ca2a8..6758bffe34 100644
> --- a/include/hw/arm/cpu.h
> +++ b/include/hw/arm/cpu.h
> @@ -25,4 +25,53 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU)
>   #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
>   #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
>   
> +enum QemuPsciConduit {
> +    QEMU_PSCI_CONDUIT_DISABLED = 0,
> +    QEMU_PSCI_CONDUIT_SMC = 1,
> +    QEMU_PSCI_CONDUIT_HVC = 2,
> +};
> +
> +/* Meanings of the ARMCPU object's four inbound GPIO lines */
> +#define ARM_CPU_IRQ 0
> +#define ARM_CPU_FIQ 1
> +#define ARM_CPU_VIRQ 2
> +#define ARM_CPU_VFIQ 3
> +
> +#define GTIMER_PHYS     0
> +#define GTIMER_VIRT     1
> +#define GTIMER_HYP      2
> +#define GTIMER_SEC      3
> +#define GTIMER_HYPVIRT  4
> +#define NUM_GTIMERS     5
> +
> +/* For M profile, some registers are banked secure vs non-secure;
> + * these are represented as a 2-element array where the first element
> + * is the non-secure copy and the second is the secure copy.
> + * When the CPU does not have implement the security extension then
> + * only the first element is used.
> + * This means that the copy for the current security state can be
> + * accessed via env->registerfield[env->v7m.secure] (whether the security
> + * extension is implemented or not).
> + */
> +enum {
> +    M_REG_NS = 0,
> +    M_REG_S = 1,
> +    M_REG_NUM_BANKS = 2,
> +};
> +
> +#define ARM_AFF0_SHIFT 0
> +#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
> +#define ARM_AFF1_SHIFT 8
> +#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
> +#define ARM_AFF2_SHIFT 16
> +#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
> +#define ARM_AFF3_SHIFT 32
> +#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
> +#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
> +
> +#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
> +#define ARM64_AFFINITY_MASK \
> +    (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
> +#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
> +
>   #endif
> diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
> index b98904b6bc..d37037e214 100644
> --- a/target/arm/cpu-qom.h
> +++ b/target/arm/cpu-qom.h
> @@ -68,19 +68,4 @@ void arm_gt_htimer_cb(void *opaque);
>   void arm_gt_stimer_cb(void *opaque);
>   void arm_gt_hvtimer_cb(void *opaque);
>   
> -#define ARM_AFF0_SHIFT 0
> -#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
> -#define ARM_AFF1_SHIFT 8
> -#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
> -#define ARM_AFF2_SHIFT 16
> -#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
> -#define ARM_AFF3_SHIFT 32
> -#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
> -#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
> -
> -#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
> -#define ARM64_AFFINITY_MASK \
> -    (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
> -#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
> -
>   #endif
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 52ac99cad3..ab6fdecf48 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -72,21 +72,6 @@
>   #define ARMV7M_EXCP_PENDSV  14
>   #define ARMV7M_EXCP_SYSTICK 15
>   
> -/* For M profile, some registers are banked secure vs non-secure;
> - * these are represented as a 2-element array where the first element
> - * is the non-secure copy and the second is the secure copy.
> - * When the CPU does not have implement the security extension then
> - * only the first element is used.
> - * This means that the copy for the current security state can be
> - * accessed via env->registerfield[env->v7m.secure] (whether the security
> - * extension is implemented or not).
> - */
> -enum {
> -    M_REG_NS = 0,
> -    M_REG_S = 1,
> -    M_REG_NUM_BANKS = 2,
> -};
> -
>   /* ARM-specific interrupt pending bits.  */
>   #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
>   #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
> @@ -107,12 +92,6 @@ enum {
>   #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
>   #endif
>   
> -/* Meanings of the ARMCPU object's four inbound GPIO lines */
> -#define ARM_CPU_IRQ 0
> -#define ARM_CPU_FIQ 1
> -#define ARM_CPU_VIRQ 2
> -#define ARM_CPU_VFIQ 3
> -
>   /* ARM-specific extra insn start words:
>    * 1: Conditional execution bits
>    * 2: Partial exception syndrome for data aborts
> @@ -160,13 +139,6 @@ typedef struct ARMGenericTimer {
>       uint64_t ctl; /* Timer Control register */
>   } ARMGenericTimer;
>   
> -#define GTIMER_PHYS     0
> -#define GTIMER_VIRT     1
> -#define GTIMER_HYP      2
> -#define GTIMER_SEC      3
> -#define GTIMER_HYPVIRT  4
> -#define NUM_GTIMERS     5
> -
>   #define VTCR_NSW (1u << 29)
>   #define VTCR_NSA (1u << 30)
>   #define VSTCR_SW VTCR_NSW
> @@ -3323,12 +3295,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env)
>   void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
>                             target_ulong *cs_base, uint32_t *flags);
>   
> -enum {
> -    QEMU_PSCI_CONDUIT_DISABLED = 0,
> -    QEMU_PSCI_CONDUIT_SMC = 1,
> -    QEMU_PSCI_CONDUIT_HVC = 2,
> -};
> -
>   #ifndef CONFIG_USER_ONLY
>   /* Return the address space index to use for a memory access */
>   static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)

[PATCH 07/18] hw/arm: Move more units to softmmu_ss[]

[Philippe Mathieu-Daudé]

The following units don't require "target/arm/cpu.h":

 - collie.c
 - gumstix.c
 - omap_sx1.c
 - z2.c

Once the header removed, we can move the units from
meson's arm_ss[] to softmmu_ss[] to build them once.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/collie.c    | 1 -
 hw/arm/gumstix.c   | 1 -
 hw/arm/meson.build | 8 ++++----
 hw/arm/omap_sx1.c  | 1 -
 hw/arm/z2.c        | 1 -
 5 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index 9edff59370..a4576feff0 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -17,7 +17,6 @@
 #include "hw/arm/boot.h"
 #include "hw/block/flash.h"
 #include "exec/address-spaces.h"
-#include "cpu.h"
 #include "qom/object.h"
 
 #define RAM_SIZE            (512 * MiB)
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
index 2ca4140c9f..3f2bcaa24e 100644
--- a/hw/arm/gumstix.c
+++ b/hw/arm/gumstix.c
@@ -44,7 +44,6 @@
 #include "hw/boards.h"
 #include "exec/address-spaces.h"
 #include "sysemu/qtest.h"
-#include "cpu.h"
 
 #define CONNEX_FLASH_SIZE   (16 * MiB)
 #define CONNEX_RAM_SIZE     (64 * MiB)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 4babaa8dfc..7c71798661 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -13,16 +13,12 @@ arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
 arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
 arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
 arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
-arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
 arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
-arm_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
 arm_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c'))
-arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
 arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
 arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
 arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
 arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
-arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
 arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
 arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
 arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c'))
@@ -62,8 +58,12 @@ arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-e
 arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c'))
 
 softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c'))
+softmmu_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
 softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
+softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c'))
+softmmu_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
 softmmu_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c'))
+softmmu_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
 
 hw_arch += {'arm': arm_ss}
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index 1d156bc344..c7ddc90d02 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -35,7 +35,6 @@
 #include "hw/block/flash.h"
 #include "sysemu/qtest.h"
 #include "exec/address-spaces.h"
-#include "cpu.h"
 #include "qemu/cutils.h"
 
 /*****************************************************************************/
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index dc25304290..610f3b5a0f 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -25,7 +25,6 @@
 #include "hw/audio/wm8750.h"
 #include "audio/audio.h"
 #include "exec/address-spaces.h"
-#include "cpu.h"
 #include "qom/object.h"
 
 #ifdef DEBUG_Z2
-- 
2.38.1

[PATCH 08/18] hw/arm: Move units to softmmu[] by replacing "{target -> hw}/arm/cpu.h"

[Philippe Mathieu-Daudé]

The following units only require the definitions exposed
by "hw/arm/cpu.", not "target/arm/cpu.h":

 - highbank.c
 - integratorcp.c
 - mainstone.c
 - musicpal.c
 - palm.c
 - spitz.c
 - strongarm.c

Once the "target/arm/cpu.h" replaced, we can move the units
from meson's arm_ss[] to softmmu_ss[] to build them once.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/highbank.c     |  2 +-
 hw/arm/integratorcp.c |  2 +-
 hw/arm/mainstone.c    |  2 +-
 hw/arm/meson.build    | 14 +++++++-------
 hw/arm/musicpal.c     |  2 +-
 hw/arm/palm.c         |  2 +-
 hw/arm/spitz.c        |  2 +-
 hw/arm/strongarm.c    |  2 +-
 8 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index f12aacea6b..5aaf2876e9 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -23,6 +23,7 @@
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "hw/arm/boot.h"
+#include "hw/arm/cpu.h"
 #include "hw/loader.h"
 #include "net/net.h"
 #include "sysemu/runstate.h"
@@ -35,7 +36,6 @@
 #include "hw/cpu/a15mpcore.h"
 #include "qemu/log.h"
 #include "qom/object.h"
-#include "cpu.h"
 
 #define SMP_BOOT_ADDR           0x100
 #define SMP_BOOT_REG            0x40
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index b109ece3ae..457db610dc 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -9,7 +9,7 @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
-#include "cpu.h"
+#include "hw/arm/cpu.h"
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "hw/boards.h"
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index 68329c4617..cb8ee05d0d 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -15,6 +15,7 @@
 #include "qemu/units.h"
 #include "qemu/error-report.h"
 #include "qapi/error.h"
+#include "hw/arm/cpu.h"
 #include "hw/arm/pxa.h"
 #include "hw/arm/boot.h"
 #include "net/net.h"
@@ -23,7 +24,6 @@
 #include "hw/block/flash.h"
 #include "hw/sysbus.h"
 #include "exec/address-spaces.h"
-#include "cpu.h"
 
 /* Device addresses */
 #define MST_FPGA_PHYS	0x08000000
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 7c71798661..f742107847 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -4,17 +4,11 @@ arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
 arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
 arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
 arm_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
-arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
-arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
-arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
 arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
-arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
 arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
 arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
 arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
 arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
-arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
-arm_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c'))
 arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
 arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
 arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
@@ -29,7 +23,6 @@ arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c'))
 arm_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c', 'pxa2xx_gpio.c', 'pxa2xx_pic.c'))
 arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c'))
 arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c'))
-arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
 arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
@@ -58,10 +51,17 @@ arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-e
 arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c'))
 
 softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c'))
+softmmu_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
 softmmu_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
 softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
 softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
+softmmu_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
+softmmu_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
+softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
+softmmu_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c'))
+softmmu_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c'))
+softmmu_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
 softmmu_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
 softmmu_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c'))
 softmmu_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index 73e2b7e4ce..07cd80bc13 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -12,7 +12,7 @@
 #include "qemu/osdep.h"
 #include "qemu/units.h"
 #include "qapi/error.h"
-#include "cpu.h"
+#include "hw/arm/cpu.h"
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "hw/arm/boot.h"
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index 68e11dd1ec..6d637d7079 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -29,7 +29,7 @@
 #include "hw/input/tsc2xxx.h"
 #include "hw/irq.h"
 #include "hw/loader.h"
-#include "cpu.h"
+#include "hw/arm/cpu.h"
 #include "qemu/cutils.h"
 #include "qom/object.h"
 
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index f732fe0acf..4628b60792 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -33,7 +33,7 @@
 #include "hw/adc/max111x.h"
 #include "migration/vmstate.h"
 #include "exec/address-spaces.h"
-#include "cpu.h"
+#include "hw/arm/cpu.h"
 #include "qom/object.h"
 
 enum spitz_model_e { spitz, akita, borzoi, terrier };
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index 39b8f01ac4..025bd38dc7 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -28,7 +28,7 @@
  */
 
 #include "qemu/osdep.h"
-#include "cpu.h"
+#include "hw/arm/cpu.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
 #include "hw/qdev-properties-system.h"
-- 
2.38.1

[PATCH 09/18] hw/arm/armv7m: Remove 'target/arm/cpu.h' from NVIC header

[Philippe Mathieu-Daudé]

"hw/intc/armv7m_nvic.h" only requires the HW definitions exposed
by the "hw/arm/cpu.h" header.

Move the "target/arm/cpu.h" header inclusion to armv7m.c which
is the single unit requiring it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/armv7m.c               | 2 ++
 include/hw/intc/armv7m_nvic.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 50a9507c0b..1e9ed1e7af 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -8,6 +8,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "hw/arm/cpu.h"
 #include "hw/arm/armv7m.h"
 #include "qapi/error.h"
 #include "hw/sysbus.h"
@@ -20,6 +21,7 @@
 #include "qemu/error-report.h"
 #include "qemu/module.h"
 #include "qemu/log.h"
+#include "target/arm/cpu.h"
 #include "target/arm/idau.h"
 #include "migration/vmstate.h"
 
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 0180c7b0ca..c0c514af63 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -10,7 +10,7 @@
 #ifndef HW_ARM_ARMV7M_NVIC_H
 #define HW_ARM_ARMV7M_NVIC_H
 
-#include "target/arm/cpu.h"
+#include "hw/arm/cpu.h"
 #include "hw/sysbus.h"
 #include "hw/timer/armv7m_systick.h"
 #include "qom/object.h"
-- 
2.38.1

[PATCH 10/18] hw/arm: Move various armv7m-related units to softmmu_ss[]

[Philippe Mathieu-Daudé]

In the previous commit we remove the indirect dependency on
"target/arm/cpu.h" from all these ARMv7-M units:

 - armsse.c
 - msf2-som.c
 - microbit.c
 - mps2-tz.c
 - mps2.c
 - msf2-soc.c
 - musca.c
 - netduino2.c
 - netduinoplus2.c
 - nrf51_soc.c
 - stellaris.c
 - stm32f100_soc.c
 - stm32f205_soc.c
 - stm32f405_soc.c
 - stm32vldiscovery.c

We can now move them to meson's softmmu_ss[] source set to
buid them once.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/meson.build | 27 +++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)

diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index f742107847..f7e1d4add6 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -3,7 +3,6 @@ arm_ss.add(files('boot.c'), fdt)
 arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
 arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
 arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
-arm_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
 arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
 arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
 arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
@@ -11,8 +10,6 @@ arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c
 arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
 arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
 arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
-arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
-arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
 arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
 arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
 arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c'))
@@ -26,9 +23,6 @@ arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
 arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
-arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
-arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
-arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
 arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
 arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c'))
 arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
@@ -40,27 +34,36 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed_ast2600.c',
   'aspeed_ast10x0.c',
   'fby35.c'))
-arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
-arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
-arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
-arm_ss.add(when: 'CONFIG_MUSCA', if_true: files('musca.c'))
-arm_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c'))
 arm_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c'))
 arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))
 arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c'))
-arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c'))
 
 softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c'))
+softmmu_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c'))
 softmmu_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
 softmmu_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
+softmmu_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
 softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
 softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
 softmmu_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
 softmmu_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
 softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
+softmmu_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
+softmmu_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
+softmmu_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
+softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
+softmmu_ss.add(when: 'CONFIG_MUSCA', if_true: files('musca.c'))
 softmmu_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
+softmmu_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
+softmmu_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
+softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c'))
 softmmu_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c'))
+softmmu_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
+softmmu_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
+softmmu_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
+softmmu_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
+softmmu_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
 softmmu_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
 softmmu_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
 softmmu_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c'))
-- 
2.38.1

[PATCH 11/18] hw/arm/digic: Remove unnecessary target_long use

[Philippe Mathieu-Daudé]

load_image_targphys(), declared in "hw/loader.h", returns a ssize_t.

Remove the 'target_long' type which size changes per target.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/digic_boards.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 4093af09cb..529d44e4e7 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -80,7 +80,7 @@ static void digic4_board_init(MachineState *machine, DigicBoard *board)
 static void digic_load_rom(DigicState *s, hwaddr addr,
                            hwaddr max_size, const char *filename)
 {
-    target_long rom_size;
+    ssize_t rom_size;
 
     if (qtest_enabled()) {
         /* qtest runs no code so don't attempt a ROM load which
-- 
2.38.1

Re: [PATCH 11/18] hw/arm/digic: Remove unnecessary target_long use

[Richard Henderson]

On 1/10/23 08:43, Philippe Mathieu-Daudé wrote:
> load_image_targphys(), declared in "hw/loader.h", returns a ssize_t.
> 
> Remove the 'target_long' type which size changes per target.
> 
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
>   hw/arm/digic_boards.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH 12/18] hw/arm/digic: Replace object_initialize(ARMCPU) by object_new(ARMCPU)

[Philippe Mathieu-Daudé]

Replace the ARMCPU field in DigicState by a reference to
an allocated ARMCPU. Instead of initializing the field
with object_initialize(), allocate it with object_new().

As we don't access ARMCPU internal fields or size, we can
move digic.c from arm_ss[] to the more generic softmmu_ss[].

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/digic.c         | 7 ++++---
 hw/arm/meson.build     | 7 ++-----
 include/hw/arm/digic.h | 4 ++--
 3 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/hw/arm/digic.c b/hw/arm/digic.c
index 6df5547977..fe24b91db6 100644
--- a/hw/arm/digic.c
+++ b/hw/arm/digic.c
@@ -36,7 +36,8 @@ static void digic_init(Object *obj)
     DigicState *s = DIGIC(obj);
     int i;
 
-    object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm946"));
+    s->cpu = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("arm946")));
+    object_property_add_child(obj, "cpu", OBJECT(s->cpu));
 
     for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
         g_autofree char *name = g_strdup_printf("timer[%d]", i);
@@ -52,12 +53,12 @@ static void digic_realize(DeviceState *dev, Error **errp)
     SysBusDevice *sbd;
     int i;
 
-    if (!object_property_set_bool(OBJECT(&s->cpu), "reset-hivecs", true,
+    if (!object_property_set_bool(OBJECT(s->cpu), "reset-hivecs", true,
                                   errp)) {
         return;
     }
 
-    if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
+    if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) {
         return;
     }
 
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index f7e1d4add6..0c7554b763 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -2,10 +2,6 @@ arm_ss = ss.source_set()
 arm_ss.add(files('boot.c'), fdt)
 arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
 arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
-arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
-arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
-arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
-arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
 arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
 arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
 arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
@@ -18,7 +14,6 @@ arm_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c'))
 arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c'))
 arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c'))
 arm_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c', 'pxa2xx_gpio.c', 'pxa2xx_pic.c'))
-arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c'))
 arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
@@ -42,6 +37,8 @@ softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c'))
 softmmu_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c'))
 softmmu_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
 softmmu_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
+softmmu_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c'))
+softmmu_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
 softmmu_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
 softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
 softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
diff --git a/include/hw/arm/digic.h b/include/hw/arm/digic.h
index 646802806e..1bfd6788c9 100644
--- a/include/hw/arm/digic.h
+++ b/include/hw/arm/digic.h
@@ -18,7 +18,7 @@
 #ifndef HW_ARM_DIGIC_H
 #define HW_ARM_DIGIC_H
 
-#include "target/arm/cpu.h"
+#include "hw/arm/cpu.h"
 #include "hw/timer/digic-timer.h"
 #include "hw/char/digic-uart.h"
 #include "qom/object.h"
@@ -34,7 +34,7 @@ struct DigicState {
     DeviceState parent_obj;
     /*< public >*/
 
-    ARMCPU cpu;
+    ARMCPU *cpu;
 
     DigicTimerState timer[DIGIC4_NB_TIMERS];
     DigicUartState uart;
-- 
2.38.1

Re: [PATCH 12/18] hw/arm/digic: Replace object_initialize(ARMCPU) by object_new(ARMCPU)

[Peter Maydell]

On Tue, 10 Jan 2023 at 16:45, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> Replace the ARMCPU field in DigicState by a reference to
> an allocated ARMCPU. Instead of initializing the field
> with object_initialize(), allocate it with object_new().
>
> As we don't access ARMCPU internal fields or size, we can
> move digic.c from arm_ss[] to the more generic softmmu_ss[].

I'm not really a fan of this, because it moves away
from a standard coding pattern we've been using for
new QOM 'container' devices, where all the sub-components
of the device are structs embedded in the device's own
struct. This is as opposed to the old style which tended
to use "allocate memory for the sub-component and have
pointers to it". It means the CPU object is now being
treated differently from all the timers, UARTs, etc.

thanks
-- PMM

Re: [PATCH 12/18] hw/arm/digic: Replace object_initialize(ARMCPU) by object_new(ARMCPU)

[Philippe Mathieu-Daudé]

On 10/1/23 17:52, Peter Maydell wrote:
> On Tue, 10 Jan 2023 at 16:45, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>>
>> Replace the ARMCPU field in DigicState by a reference to
>> an allocated ARMCPU. Instead of initializing the field
>> with object_initialize(), allocate it with object_new().
>>
>> As we don't access ARMCPU internal fields or size, we can
>> move digic.c from arm_ss[] to the more generic softmmu_ss[].
> 
> I'm not really a fan of this, because it moves away
> from a standard coding pattern we've been using for
> new QOM 'container' devices, where all the sub-components
> of the device are structs embedded in the device's own
> struct. This is as opposed to the old style which tended
> to use "allocate memory for the sub-component and have
> pointers to it". It means the CPU object is now being
> treated differently from all the timers, UARTs, etc.

OK, at least you don't object on patches 1-11/13 :)

I might still post the other parts of this current approach to not
lose them in case I can't find a better way.

Thanks,

Phil.

Re: [PATCH 12/18] hw/arm/digic: Replace object_initialize(ARMCPU) by object_new(ARMCPU)

[Alex Bennée]

Peter Maydell <peter.maydell@linaro.org> writes:

> On Tue, 10 Jan 2023 at 16:45, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>>
>> Replace the ARMCPU field in DigicState by a reference to
>> an allocated ARMCPU. Instead of initializing the field
>> with object_initialize(), allocate it with object_new().
>>
>> As we don't access ARMCPU internal fields or size, we can
>> move digic.c from arm_ss[] to the more generic softmmu_ss[].
>
> I'm not really a fan of this, because it moves away
> from a standard coding pattern we've been using for
> new QOM 'container' devices, where all the sub-components
> of the device are structs embedded in the device's own
> struct. This is as opposed to the old style which tended
> to use "allocate memory for the sub-component and have
> pointers to it". It means the CPU object is now being
> treated differently from all the timers, UARTs, etc.

I think you can certainly make the argument that CPU's have always been
treated separately because we pass it around as an anonymous pointer all
the time. We currently can't support two concrete CPU types in the same
structure. For example zyncmp has:

  struct XlnxZynqMPState {
      /*< private >*/
      DeviceState parent_obj;

      /*< public >*/
      CPUClusterState apu_cluster;
      CPUClusterState rpu_cluster;
      ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
      ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];

which only works because A/R cpus are the same underlying type. However
when we want to add Microblaze how would we do it?

Is the main problem preventing us from including multiple cpu.h
definitions that we overload CPUArch and CPUArchState? What are the
implications if we convert them to fully anonymous pointer types?

>
> thanks
> -- PMM


-- 
Alex Bennée
Virtualisation Tech Lead @ Linaro

Re: [PATCH 12/18] hw/arm/digic: Replace object_initialize(ARMCPU) by object_new(ARMCPU)

[Peter Maydell]

On Wed, 25 Jan 2023 at 12:14, Alex Bennée <alex.bennee@linaro.org> wrote:
> Peter Maydell <peter.maydell@linaro.org> writes:
> > I'm not really a fan of this, because it moves away
> > from a standard coding pattern we've been using for
> > new QOM 'container' devices, where all the sub-components
> > of the device are structs embedded in the device's own
> > struct. This is as opposed to the old style which tended
> > to use "allocate memory for the sub-component and have
> > pointers to it". It means the CPU object is now being
> > treated differently from all the timers, UARTs, etc.
>
> I think you can certainly make the argument that CPU's have always been
> treated separately because we pass it around as an anonymous pointer all
> the time. We currently can't support two concrete CPU types in the same
> structure. For example zyncmp has:
>
>   struct XlnxZynqMPState {
>       /*< private >*/
>       DeviceState parent_obj;
>
>       /*< public >*/
>       CPUClusterState apu_cluster;
>       CPUClusterState rpu_cluster;
>       ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
>       ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
>
> which only works because A/R cpus are the same underlying type. However
> when we want to add Microblaze how would we do it?

You'd add fields
    MicroBlazeCPU other_cpu;

As you note, at the moment that doesn't work because cpu.h
is magic and embeds an assumption that it's only included
in compile-per-target objects and therefore any given source
file only includes one of them at once. I think we should be
aiming to remove those assumptions, not work around them.

thanks
-- PMM

[PATCH 13/18] hw/arm/fsl-imx: Correct GPIO/GPT index in QOM tree

[Philippe Mathieu-Daudé]

GPT and GPIO are numbered from #1.

Fixes: 757282ada8 ("i.MX: Add i.MX7 SOC.")
Fixes: 31cbf933f0 ("i.MX: Add i.MX6UL SOC")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/fsl-imx6ul.c | 4 ++--
 hw/arm/fsl-imx7.c   | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index d88d6cc1c5..568317117c 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -72,7 +72,7 @@ static void fsl_imx6ul_init(Object *obj)
      * GPIOs 1 to 5
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
-        snprintf(name, NAME_SIZE, "gpio%d", i);
+        snprintf(name, NAME_SIZE, "gpio%d", i + 1);
         object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
     }
 
@@ -80,7 +80,7 @@ static void fsl_imx6ul_init(Object *obj)
      * GPT 1, 2
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
-        snprintf(name, NAME_SIZE, "gpt%d", i);
+        snprintf(name, NAME_SIZE, "gpt%d", i + 1);
         object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT);
     }
 
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index afc7480799..6115677d43 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -52,7 +52,7 @@ static void fsl_imx7_init(Object *obj)
      * GPIOs 1 to 7
      */
     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
-        snprintf(name, NAME_SIZE, "gpio%d", i);
+        snprintf(name, NAME_SIZE, "gpio%d", i + 1);
         object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
     }
 
@@ -60,7 +60,7 @@ static void fsl_imx7_init(Object *obj)
      * GPT1, 2, 3, 4
      */
     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
-        snprintf(name, NAME_SIZE, "gpt%d", i);
+        snprintf(name, NAME_SIZE, "gpt%d", i + 1);
         object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
     }
 
-- 
2.38.1

Re: [PATCH 13/18] hw/arm/fsl-imx: Correct GPIO/GPT index in QOM tree

[Philippe Mathieu-Daudé]

On 10/1/23 17:44, Philippe Mathieu-Daudé wrote:
> GPT and GPIO are numbered from #1.
> 
> Fixes: 757282ada8 ("i.MX: Add i.MX7 SOC.")
> Fixes: 31cbf933f0 ("i.MX: Add i.MX6UL SOC")
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/arm/fsl-imx6ul.c | 4 ++--
>   hw/arm/fsl-imx7.c   | 4 ++--
>   2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
> index d88d6cc1c5..568317117c 100644
> --- a/hw/arm/fsl-imx6ul.c
> +++ b/hw/arm/fsl-imx6ul.c
> @@ -72,7 +72,7 @@ static void fsl_imx6ul_init(Object *obj)
>        * GPIOs 1 to 5

FWIW it is even  ^^^^^^ commented.

>        */
>       for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
> -        snprintf(name, NAME_SIZE, "gpio%d", i);
> +        snprintf(name, NAME_SIZE, "gpio%d", i + 1);
>           object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
>       }
>   
> @@ -80,7 +80,7 @@ static void fsl_imx6ul_init(Object *obj)
>        * GPT 1, 2

                ^^^^

>        */
>       for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
> -        snprintf(name, NAME_SIZE, "gpt%d", i);
> +        snprintf(name, NAME_SIZE, "gpt%d", i + 1);
>           object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT);
>       }
>   
> diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
> index afc7480799..6115677d43 100644
> --- a/hw/arm/fsl-imx7.c
> +++ b/hw/arm/fsl-imx7.c
> @@ -52,7 +52,7 @@ static void fsl_imx7_init(Object *obj)
>        * GPIOs 1 to 7

                  ^^^^^^

>        */
>       for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
> -        snprintf(name, NAME_SIZE, "gpio%d", i);
> +        snprintf(name, NAME_SIZE, "gpio%d", i + 1);
>           object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
>       }
>   
> @@ -60,7 +60,7 @@ static void fsl_imx7_init(Object *obj)
>        * GPT1, 2, 3, 4

               ^^^^^^^^^^

>        */
>       for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
> -        snprintf(name, NAME_SIZE, "gpt%d", i);
> +        snprintf(name, NAME_SIZE, "gpt%d", i + 1);
>           object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
>       }
>   

[PATCH 14/18] hw/arm/fsl-imx25: Replace object_initialize(ARMCPU) by object_new()

[Philippe Mathieu-Daudé]

Replace the ARMCPU field in FslIMX25State by a reference to
an allocated ARMCPU. Instead of initializing the field with
object_initialize(), allocate it with object_new().

As we don't access ARMCPU internal fields or size, we can
move from arm_ss[] to the more generic softmmu_ss[] the followin
units:

 - fsl-imx25.c
 - imx25_pdk.c

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/fsl-imx25.c         | 9 +++++----
 hw/arm/imx25_pdk.c         | 2 +-
 hw/arm/meson.build         | 2 +-
 include/hw/arm/fsl-imx25.h | 4 ++--
 4 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
index 24c4374590..5213c1ac23 100644
--- a/hw/arm/fsl-imx25.c
+++ b/hw/arm/fsl-imx25.c
@@ -36,7 +36,8 @@ static void fsl_imx25_init(Object *obj)
     FslIMX25State *s = FSL_IMX25(obj);
     int i;
 
-    object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm926"));
+    s->cpu = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("arm926")));
+    object_property_add_child(obj, "cpu", OBJECT(s->cpu));
 
     object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC);
 
@@ -83,7 +84,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
     uint8_t i;
     Error *err = NULL;
 
-    if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
+    if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) {
         return;
     }
 
@@ -92,9 +93,9 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
-                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
+                       qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
-                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
+                       qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
 
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
         return;
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index b4f7f4e8a7..26fc0ef5ae 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -136,7 +136,7 @@ static void imx25_pdk_init(MachineState *machine)
      * fail.
      */
     if (!qtest_enabled()) {
-        arm_load_kernel(&s->soc.cpu, machine, &imx25_pdk_binfo);
+        arm_load_kernel(s->soc.cpu, machine, &imx25_pdk_binfo);
     }
 }
 
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 0c7554b763..ccda1f5149 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -20,7 +20,6 @@ arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orange
 arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
 arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
 arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c'))
-arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
 arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
 arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
 arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
@@ -41,6 +40,7 @@ softmmu_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c'))
 softmmu_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
 softmmu_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
 softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
+softmmu_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
 softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
 softmmu_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
 softmmu_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
index 1b1086e945..9ad95073c2 100644
--- a/include/hw/arm/fsl-imx25.h
+++ b/include/hw/arm/fsl-imx25.h
@@ -31,7 +31,7 @@
 #include "hw/usb/chipidea.h"
 #include "hw/watchdog/wdt_imx2.h"
 #include "exec/memory.h"
-#include "target/arm/cpu.h"
+#include "hw/arm/cpu.h"
 #include "qom/object.h"
 
 #define TYPE_FSL_IMX25 "fsl-imx25"
@@ -50,7 +50,7 @@ struct FslIMX25State {
     DeviceState parent_obj;
 
     /*< public >*/
-    ARMCPU         cpu;
+    ARMCPU         *cpu;
     IMXAVICState   avic;
     IMX25CCMState  ccm;
     IMXSerialState uart[FSL_IMX25_NUM_UARTS];
-- 
2.38.1

[PATCH 15/18] hw/arm/fsl-imx31: Replace object_initialize(ARMCPU) by object_new()

[Philippe Mathieu-Daudé]

Replace the ARMCPU field in FslIMX25State by a reference to
an allocated ARMCPU. Instead of initializing the field with
object_initialize(), allocate it with object_new().

As we don't access ARMCPU internal fields or size, we can
move from arm_ss[] to the more generic softmmu_ss[] the followin
units:

 - fsl-imx31.c
 - kzm.c

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/fsl-imx31.c         | 9 +++++----
 hw/arm/kzm.c               | 2 +-
 hw/arm/meson.build         | 2 +-
 include/hw/arm/fsl-imx31.h | 4 ++--
 4 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
index def27bb913..26c6bb67f0 100644
--- a/hw/arm/fsl-imx31.c
+++ b/hw/arm/fsl-imx31.c
@@ -32,7 +32,8 @@ static void fsl_imx31_init(Object *obj)
     FslIMX31State *s = FSL_IMX31(obj);
     int i;
 
-    object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm1136"));
+    s->cpu = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("arm1136")));
+    object_property_add_child(obj, "cpu", OBJECT(s->cpu));
 
     object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC);
 
@@ -65,7 +66,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
     uint16_t i;
     Error *err = NULL;
 
-    if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
+    if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) {
         return;
     }
 
@@ -74,9 +75,9 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
-                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
+                       qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
-                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
+                       qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
 
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
         return;
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index b1b281c9ac..8c6cdb06f5 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -126,7 +126,7 @@ static void kzm_init(MachineState *machine)
     kzm_binfo.ram_size = machine->ram_size;
 
     if (!qtest_enabled()) {
-        arm_load_kernel(&s->soc.cpu, machine, &kzm_binfo);
+        arm_load_kernel(s->soc.cpu, machine, &kzm_binfo);
     }
 }
 
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index ccda1f5149..b244db5962 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -20,7 +20,6 @@ arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orange
 arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
 arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
 arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c'))
-arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
 arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
 arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed_soc.c',
@@ -41,6 +40,7 @@ softmmu_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
 softmmu_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
 softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
 softmmu_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
+softmmu_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
 softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
 softmmu_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
 softmmu_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
index c116a73e0b..c117136901 100644
--- a/include/hw/arm/fsl-imx31.h
+++ b/include/hw/arm/fsl-imx31.h
@@ -27,7 +27,7 @@
 #include "hw/gpio/imx_gpio.h"
 #include "hw/watchdog/wdt_imx2.h"
 #include "exec/memory.h"
-#include "target/arm/cpu.h"
+#include "hw/arm/cpu.h"
 #include "qom/object.h"
 
 #define TYPE_FSL_IMX31 "fsl-imx31"
@@ -43,7 +43,7 @@ struct FslIMX31State {
     DeviceState parent_obj;
 
     /*< public >*/
-    ARMCPU         cpu;
+    ARMCPU         *cpu;
     IMXAVICState   avic;
     IMX31CCMState  ccm;
     IMXSerialState uart[FSL_IMX31_NUM_UARTS];
-- 
2.38.1

[PATCH 16/18] hw/arm/fsl-imx7: Replace object_initialize(ARMCPU) by object_new()

[Philippe Mathieu-Daudé]

Replace the ARMCPU field in FslIMX7State by a reference to
an allocated ARMCPU. Instead of initializing the field with
object_initialize(), allocate it with object_new().

As we don't access ARMCPU internal fields or size, we can
move from arm_ss[] to the more generic softmmu_ss[] the followin
units:

 - fsl-imx7.c
 - mcimx7d-sabre.c

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/fsl-imx7.c         | 6 +++---
 hw/arm/mcimx7d-sabre.c    | 2 +-
 hw/arm/meson.build        | 2 +-
 include/hw/arm/fsl-imx7.h | 4 ++--
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index 6115677d43..634ed299cc 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -38,8 +38,8 @@ static void fsl_imx7_init(Object *obj)
 
     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
         snprintf(name, NAME_SIZE, "cpu%d", i);
-        object_initialize_child(obj, name, &s->cpu[i],
-                                ARM_CPU_TYPE_NAME("cortex-a7"));
+        s->cpu[i] = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("cortex-a7")));
+        object_property_add_child(obj, name, OBJECT(s->cpu[i]));
     }
 
     /*
@@ -157,7 +157,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     for (i = 0; i < smp_cpus; i++) {
-        o = OBJECT(&s->cpu[i]);
+        o = OBJECT(s->cpu[i]);
 
         /* On uniprocessor, the CBAR is set to 0 */
         if (smp_cpus > 1) {
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index 6182b15f19..ad46bf79c6 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -61,7 +61,7 @@ static void mcimx7d_sabre_init(MachineState *machine)
     }
 
     if (!qtest_enabled()) {
-        arm_load_kernel(&s->cpu[0], machine, &boot_info);
+        arm_load_kernel(s->cpu[0], machine, &boot_info);
     }
 }
 
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index b244db5962..53ce301cbe 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -27,7 +27,6 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed_ast2600.c',
   'aspeed_ast10x0.c',
   'fby35.c'))
-arm_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c'))
 arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))
 arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c'))
 
@@ -41,6 +40,7 @@ softmmu_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
 softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
 softmmu_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
 softmmu_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
+softmmu_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c'))
 softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
 softmmu_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
 softmmu_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index ed8c1ec813..97c9731db3 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -38,7 +38,7 @@
 #include "hw/net/imx_fec.h"
 #include "hw/pci-host/designware.h"
 #include "hw/usb/chipidea.h"
-#include "target/arm/cpu.h"
+#include "hw/arm/cpu.h"
 #include "qom/object.h"
 
 #define TYPE_FSL_IMX7 "fsl-imx7"
@@ -65,7 +65,7 @@ struct FslIMX7State {
     DeviceState    parent_obj;
 
     /*< public >*/
-    ARMCPU             cpu[FSL_IMX7_NUM_CPUS];
+    ARMCPU             *cpu[FSL_IMX7_NUM_CPUS];
     A15MPPrivState     a7mpcore;
     IMXGPTState        gpt[FSL_IMX7_NUM_GPTS];
     IMXGPIOState       gpio[FSL_IMX7_NUM_GPIOS];
-- 
2.38.1

[PATCH 17/18] hw/arm/fsl-imx6: Replace object_initialize(ARMCPU) by object_new()

[Philippe Mathieu-Daudé]

Replace the ARMCPU field in FslIMX6[UL]State by a reference
to an allocated ARMCPU. Instead of initializing the field with
object_initialize(), allocate it with object_new().

As we don't access ARMCPU internal fields or size, we can
move from arm_ss[] to the more generic softmmu_ss[] the followin
units:

 - fsl-imx6.c
 - fsl-imx6ul.c
 - mcimx6ul-evk.c
 - sabrelite.c

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/fsl-imx6.c           | 14 +++++++-------
 hw/arm/fsl-imx6ul.c         |  8 ++++----
 hw/arm/mcimx6ul-evk.c       |  2 +-
 hw/arm/meson.build          |  6 +++---
 hw/arm/sabrelite.c          |  2 +-
 include/hw/arm/fsl-imx6.h   |  4 ++--
 include/hw/arm/fsl-imx6ul.h |  4 ++--
 7 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index 00dafe3f62..085cd3b1c8 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -43,8 +43,8 @@ static void fsl_imx6_init(Object *obj)
 
     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
         snprintf(name, NAME_SIZE, "cpu%d", i);
-        object_initialize_child(obj, name, &s->cpu[i],
-                                ARM_CPU_TYPE_NAME("cortex-a9"));
+        s->cpu[i] = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("cortex-a9")));
+        object_property_add_child(obj, name, OBJECT(s->cpu[i]));
     }
 
     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
@@ -120,17 +120,17 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
 
         /* On uniprocessor, the CBAR is set to 0 */
         if (smp_cpus > 1) {
-            object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
+            object_property_set_int(OBJECT(s->cpu[i]), "reset-cbar",
                                     FSL_IMX6_A9MPCORE_ADDR, &error_abort);
         }
 
         /* All CPU but CPU 0 start in power off mode */
         if (i) {
-            object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off",
+            object_property_set_bool(OBJECT(s->cpu[i]), "start-powered-off",
                                      true, &error_abort);
         }
 
-        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
+        if (!qdev_realize(DEVICE(s->cpu[i]), NULL, errp)) {
             return;
         }
     }
@@ -148,9 +148,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
 
     for (i = 0; i < smp_cpus; i++) {
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
-                           qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
+                           qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
-                           qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
+                           qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_FIQ));
     }
 
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index 568317117c..be0573a243 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -34,8 +34,8 @@ static void fsl_imx6ul_init(Object *obj)
     char name[NAME_SIZE];
     int i;
 
-    object_initialize_child(obj, "cpu0", &s->cpu,
-                            ARM_CPU_TYPE_NAME("cortex-a7"));
+    s->cpu = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("cortex-a7")));
+    object_property_add_child(obj, "cpu0", OBJECT(s->cpu));
 
     /*
      * A7MPCORE
@@ -166,7 +166,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
         return;
     }
 
-    qdev_realize(DEVICE(&s->cpu), NULL, &error_abort);
+    qdev_realize(DEVICE(s->cpu), NULL, &error_abort);
 
     /*
      * A7MPCORE
@@ -178,7 +178,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
 
     sbd = SYS_BUS_DEVICE(&s->a7mpcore);
-    d = DEVICE(&s->cpu);
+    d = DEVICE(s->cpu);
 
     sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ));
     sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ));
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index d83c3c380e..89a65e4c4b 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -61,7 +61,7 @@ static void mcimx6ul_evk_init(MachineState *machine)
     }
 
     if (!qtest_enabled()) {
-        arm_load_kernel(&s->cpu, machine, &boot_info);
+        arm_load_kernel(s->cpu, machine, &boot_info);
     }
 }
 
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 53ce301cbe..a7ee21e32f 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -9,7 +9,6 @@ arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
 arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
 arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
 arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c'))
-arm_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c'))
 
 arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c'))
 arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c'))
@@ -20,7 +19,6 @@ arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orange
 arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
 arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
 arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c'))
-arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
 arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed_soc.c',
   'aspeed.c',
@@ -28,7 +26,6 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed_ast10x0.c',
   'fby35.c'))
 arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))
-arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c'))
 
 softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c'))
 softmmu_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c'))
@@ -40,6 +37,8 @@ softmmu_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
 softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
 softmmu_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
 softmmu_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
+softmmu_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
+softmmu_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c'))
 softmmu_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c'))
 softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
 softmmu_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
@@ -55,6 +54,7 @@ softmmu_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
 softmmu_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
 softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c'))
+softmmu_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c'))
 softmmu_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c'))
 softmmu_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
 softmmu_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
index 41191245b8..acd1d344b9 100644
--- a/hw/arm/sabrelite.c
+++ b/hw/arm/sabrelite.c
@@ -98,7 +98,7 @@ static void sabrelite_init(MachineState *machine)
     sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
 
     if (!qtest_enabled()) {
-        arm_load_kernel(&s->cpu[0], machine, &sabrelite_binfo);
+        arm_load_kernel(s->cpu[0], machine, &sabrelite_binfo);
     }
 }
 
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index 9d24d98189..ba42047b21 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -32,8 +32,8 @@
 #include "hw/net/imx_fec.h"
 #include "hw/usb/chipidea.h"
 #include "hw/usb/imx-usb-phy.h"
+#include "hw/arm/cpu.h"
 #include "exec/memory.h"
-#include "target/arm/cpu.h"
 #include "qom/object.h"
 
 #define TYPE_FSL_IMX6 "fsl-imx6"
@@ -55,7 +55,7 @@ struct FslIMX6State {
     DeviceState parent_obj;
 
     /*< public >*/
-    ARMCPU         cpu[FSL_IMX6_NUM_CPUS];
+    ARMCPU         *cpu[FSL_IMX6_NUM_CPUS];
     A9MPPrivState  a9mpcore;
     IMX6CCMState   ccm;
     IMX6SRCState   src;
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index 4f42fe4192..f49d0c9b83 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -37,7 +37,7 @@
 #include "hw/usb/chipidea.h"
 #include "hw/usb/imx-usb-phy.h"
 #include "exec/memory.h"
-#include "target/arm/cpu.h"
+#include "hw/arm/cpu.h"
 #include "qom/object.h"
 
 #define TYPE_FSL_IMX6UL "fsl-imx6ul"
@@ -66,7 +66,7 @@ struct FslIMX6ULState {
     DeviceState    parent_obj;
 
     /*< public >*/
-    ARMCPU             cpu;
+    ARMCPU             *cpu;
     A15MPPrivState     a7mpcore;
     IMXGPTState        gpt[FSL_IMX6UL_NUM_GPTS];
     IMXEPITState       epit[FSL_IMX6UL_NUM_EPITS];
-- 
2.38.1

[PATCH 18/18] hw/arm/allwinner: Replace object_initialize(ARMCPU) by object_new()

[Philippe Mathieu-Daudé]

Replace the ARMCPU field in both AwA10State / AwH3State by a
reference to an allocated ARMCPU. Instead of initializing the
field with object_initialize(), allocate it with object_new().

As we don't access ARMCPU internal fields or size, we can
move from arm_ss[] to the more generic softmmu_ss[] the followin
units:

 - allwinner-a10.c
 - allwinner-h3.c
 - cubieboard.c
 - orangepi.c

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/allwinner-a10.c         | 10 +++++-----
 hw/arm/allwinner-h3.c          | 14 +++++++-------
 hw/arm/cubieboard.c            |  2 +-
 hw/arm/meson.build             |  4 ++--
 include/hw/arm/allwinner-a10.h |  4 ++--
 include/hw/arm/allwinner-h3.h  |  4 ++--
 6 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 79082289ea..685673e7bd 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -39,8 +39,8 @@ static void aw_a10_init(Object *obj)
 {
     AwA10State *s = AW_A10(obj);
 
-    object_initialize_child(obj, "cpu", &s->cpu,
-                            ARM_CPU_TYPE_NAME("cortex-a8"));
+    s->cpu = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("cortex-a8")));
+    object_property_add_child(obj, "cpu", OBJECT(s->cpu));
 
     object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);
 
@@ -71,7 +71,7 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
     AwA10State *s = AW_A10(dev);
     SysBusDevice *sysbusdev;
 
-    if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
+    if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) {
         return;
     }
 
@@ -81,9 +81,9 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
     sysbusdev = SYS_BUS_DEVICE(&s->intc);
     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
     sysbus_connect_irq(sysbusdev, 0,
-                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
+                       qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
     sysbus_connect_irq(sysbusdev, 1,
-                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
+                       qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
     qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
 
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 308ed15552..1409101b3a 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -192,8 +192,8 @@ static void allwinner_h3_init(Object *obj)
     s->memmap = allwinner_h3_memmap;
 
     for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
-        object_initialize_child(obj, "cpu[*]", &s->cpus[i],
-                                ARM_CPU_TYPE_NAME("cortex-a7"));
+        s->cpus[i] = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("cortex-a7")));
+        object_property_add_child(obj, "cpu[*]", OBJECT(s->cpus[i]));
     }
 
     object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
@@ -239,15 +239,15 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
          * Disable secondary CPUs. Guest EL3 firmware will start
          * them via CPU reset control registers.
          */
-        qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
+        qdev_prop_set_bit(DEVICE(s->cpus[i]), "start-powered-off",
                           i > 0);
 
         /* All exception levels required */
-        qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
-        qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
+        qdev_prop_set_bit(DEVICE(s->cpus[i]), "has_el3", true);
+        qdev_prop_set_bit(DEVICE(s->cpus[i]), "has_el2", true);
 
         /* Mark realized */
-        qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal);
+        qdev_realize(DEVICE(s->cpus[i]), NULL, &error_fatal);
     }
 
     /* Generic Interrupt Controller */
@@ -270,7 +270,7 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
      * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
      */
     for (i = 0; i < AW_H3_NUM_CPUS; i++) {
-        DeviceState *cpudev = DEVICE(&s->cpus[i]);
+        DeviceState *cpudev = DEVICE(s->cpus[i]);
         int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
         int irq;
         /*
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index 5e3372a3c7..fcb366d4ac 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -96,7 +96,7 @@ static void cubieboard_init(MachineState *machine)
     /* TODO create and connect IDE devices for ide_drive_get() */
 
     cubieboard_binfo.ram_size = machine->ram_size;
-    arm_load_kernel(&a10->cpu, machine, &cubieboard_binfo);
+    arm_load_kernel(a10->cpu, machine, &cubieboard_binfo);
 }
 
 static void cubieboard_machine_init(MachineClass *mc)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index a7ee21e32f..06c9f1c86b 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -14,8 +14,6 @@ arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c'))
 arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c'))
 arm_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c', 'pxa2xx_gpio.c', 'pxa2xx_pic.c'))
 arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c'))
-arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
-arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
 arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
 arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
 arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c'))
@@ -27,6 +25,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'fby35.c'))
 arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))
 
+softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
+softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
 softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c'))
 softmmu_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c'))
 softmmu_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index f9240ffa64..3a3ccc390f 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -13,8 +13,8 @@
 #include "hw/usb/hcd-ohci.h"
 #include "hw/usb/hcd-ehci.h"
 #include "hw/rtc/allwinner-rtc.h"
+#include "hw/arm/cpu.h"
 
-#include "target/arm/cpu.h"
 #include "qom/object.h"
 
 
@@ -30,7 +30,7 @@ struct AwA10State {
     DeviceState parent_obj;
     /*< public >*/
 
-    ARMCPU cpu;
+    ARMCPU *cpu;
     AwA10PITState timer;
     AwA10PICState intc;
     AwEmacState emac;
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index 63025fb27c..5e8be4392e 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -47,7 +47,7 @@
 #include "hw/sd/allwinner-sdhost.h"
 #include "hw/net/allwinner-sun8i-emac.h"
 #include "hw/rtc/allwinner-rtc.h"
-#include "target/arm/cpu.h"
+#include "hw/arm/cpu.h"
 #include "sysemu/block-backend.h"
 
 /**
@@ -121,7 +121,7 @@ struct AwH3State {
     DeviceState parent_obj;
     /*< public >*/
 
-    ARMCPU cpus[AW_H3_NUM_CPUS];
+    ARMCPU *cpus[AW_H3_NUM_CPUS];
     const hwaddr *memmap;
     AwA10PITState timer;
     AwH3ClockCtlState ccu;
-- 
2.38.1