From: Richard Henderson <richard.henderson@linaro.org>
To: Song Gao <gaosong@loongson.cn>, qemu-devel@nongnu.org
Cc: yangxiaojuan@loongson.cn, huqi@loongson.cn,
peter.maydell@linaro.org, alex.bennee@linaro.org,
maobibo@loongson.cn
Subject: Re: [PATCH v2 1/4] target/loongarch: ftint_xxx insns set the result high 32bit 0xffffffff
Date: Wed, 28 Sep 2022 08:14:48 -0700 [thread overview]
Message-ID: <7cedbe66-7fc0-9e4a-c6e1-55aeb76c3e42@linaro.org> (raw)
In-Reply-To: <20220927064838.3570928-2-gaosong@loongson.cn>
On 9/26/22 23:48, Song Gao wrote:
> we just set high 32bit 0xffffffff as the other float instructions do.
>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
> target/loongarch/fpu_helper.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
But the result in these cases is an integer, not a (single-precision) float.
Is this really what hardware does?
r~
next prev parent reply other threads:[~2022-09-28 16:59 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-27 6:48 [PATCH v2 0/4] Fix some loongarch tcg bugs Song Gao
2022-09-27 6:48 ` [PATCH v2 1/4] target/loongarch: ftint_xxx insns set the result high 32bit 0xffffffff Song Gao
2022-09-28 15:14 ` Richard Henderson [this message]
2022-09-29 3:24 ` gaosong
2022-09-27 6:48 ` [PATCH v2 2/4] target/loongarch: bstrins.w need set dest register EXT_SIGN Song Gao
2022-09-28 15:13 ` Richard Henderson
2022-09-29 7:27 ` gaosong
2022-09-29 15:14 ` Richard Henderson
2022-09-27 6:48 ` [PATCH v2 3/4] target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags Song Gao
2022-09-28 15:16 ` Richard Henderson
2022-09-27 6:48 ` [PATCH v2 4/4] target/loongarch: flogb_{s/d} add set float_flag_divbyzero Song Gao
2022-09-28 15:24 ` Richard Henderson
2022-09-29 7:27 ` gaosong
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