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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, alistair.francis@wdc.com
Subject: Re: [PATCH 08/26] target/riscv: store RISCVCPUDef struct directly in the class
Date: Mon, 28 Apr 2025 17:20:53 +0200	[thread overview]
Message-ID: <7cf90706-05e8-40b7-aef5-108c2d7234df@linaro.org> (raw)
In-Reply-To: <CABgObfZX1j4N=Oeq9Y=_YeccCq7--s0=r5DaANA+iA1UnoJyVg@mail.gmail.com>

On 28/4/25 14:17, Paolo Bonzini wrote:
> On Mon, Apr 28, 2025 at 1:50 PM Daniel Henrique Barboza
> <dbarboza@ventanamicro.com> wrote:
>>
>>
>>
>> On 4/28/25 4:34 AM, Paolo Bonzini wrote:
>>> Prepare for adding more fields to RISCVCPUDef and reading them in
>>> riscv_cpu_init: instead of storing the misa_mxl_max field in
>>> RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct
>>> and go through it.
>>>
>>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>>> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>>> ---
>>>    target/riscv/cpu.h         |  2 +-
>>>    hw/riscv/boot.c            |  2 +-
>>>    target/riscv/cpu.c         | 23 ++++++++++++++++++-----
>>>    target/riscv/gdbstub.c     |  6 +++---
>>>    target/riscv/kvm/kvm-cpu.c | 21 +++++++++------------
>>>    target/riscv/machine.c     |  2 +-
>>>    target/riscv/tcg/tcg-cpu.c | 10 +++++-----
>>>    target/riscv/translate.c   |  2 +-
>>>    8 files changed, 39 insertions(+), 29 deletions(-)


>> Are we sure this patch compiles?
> 
> No, you're right; I was not aware that RISC-V KVM is not covered by
> CI. I'm sorry.

I remember doing it and Daniel reviewed it...:
https://lore.kernel.org/qemu-devel/20230703183145.24779-1-philmd@linaro.org/

I suppose the shame is on me for not insisting getting it merged,
wasting my own time.


  reply	other threads:[~2025-04-28 15:21 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-28  7:34 [PATCH v4 00/26] target/riscv: SATP mode and CPU definition overhaul Paolo Bonzini
2025-04-28  7:34 ` [PATCH 01/26] hw/riscv: acpi: only create RHCT MMU entry for supported types Paolo Bonzini
2025-04-28  7:34 ` [PATCH 02/26] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-04-28  7:34 ` [PATCH 03/26] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-04-28  7:34 ` [PATCH 04/26] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-04-28  7:34 ` [PATCH 05/26] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-04-28  7:34 ` [PATCH 06/26] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-04-28  7:34 ` [PATCH 07/26] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-04-28  7:34 ` [PATCH 08/26] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-04-28 11:50   ` Daniel Henrique Barboza
2025-04-28 12:17     ` Paolo Bonzini
2025-04-28 15:20       ` Philippe Mathieu-Daudé [this message]
2025-04-28 19:26         ` Paolo Bonzini
2025-04-28 14:58     ` Richard Henderson
2025-04-28  7:34 ` [PATCH 09/26] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-04-28  7:34 ` [PATCH 10/26] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-04-28  7:34 ` [PATCH 11/26] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-04-28  7:34 ` [PATCH 12/26] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-04-28  7:34 ` [PATCH 13/26] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-04-28  7:34 ` [PATCH 14/26] target/riscv: convert profile CPU models " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 15/26] target/riscv: convert bare " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 16/26] target/riscv: convert dynamic " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 17/26] target/riscv: convert SiFive E " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 18/26] target/riscv: convert ibex " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 19/26] target/riscv: convert SiFive U " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 20/26] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-04-28  7:34 ` [PATCH 21/26] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-04-28  7:34 ` [PATCH 22/26] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-04-29  4:23   ` Joel Stanley
2025-04-28  7:34 ` [PATCH 23/26] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 24/26] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 25/26] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 26/26] target/riscv: remove .instance_post_init Paolo Bonzini

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