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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id j6-20020a5d6186000000b003090cb7a9e6sm6994817wru.31.2023.05.15.01.37.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 May 2023 01:37:20 -0700 (PDT) Message-ID: <7d08b3da-b2b1-1a54-8aed-aa3aa9df4b34@redhat.com> Date: Mon, 15 May 2023 10:37:19 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [RFC PATCH v3 02/10] hw/arm/smmuv3: Update translation config to hold stage-2 Content-Language: en-US To: Mostafa Saleh , qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org References: <20230401104953.1325983-1-smostafa@google.com> <20230401104953.1325983-3-smostafa@google.com> From: Eric Auger In-Reply-To: <20230401104953.1325983-3-smostafa@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.93, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Mostafa, On 4/1/23 12:49, Mostafa Saleh wrote: > In preparation for adding stage-2 support, add a S2 config > struct(SMMUS2Cfg), composed of the following fields and embedded in > the main SMMUTransCfg: > -tsz: Size of IPA input region (S2T0SZ) > -sl0: Start level of translation (S2SL0) > -affd: AF Fault Disable (S2AFFD) > -record_faults: Record fault events (S2R) > -granule_sz: Granule page shift (based on S2TG) > -vmid: Virtual Machine ID (S2VMID) > -vttb: Address of translation table base (S2TTB) > -eff_ps: Effective PA output range (based on S2PS) > > They will be used in the next patches in stage-2 address translation. > > The fields in SMMUS2Cfg, are reordered to make the shared and stage-1 > fields next to each other, this reordering didn't change the struct > size (104 bytes before and after). > > Stage-1 only fields: aa64, asid, tt, ttb, tbi, record_faults, oas. > oas is stage-1 output address size. However, it is used to check > input address in case stage-1 is unimplemented or bypassed according > to SMMUv3 manual IHI0070.E "3.4. Address sizes" > > Shared fields: stage, disabled, bypassed, aborted, iotlb_*. > > No functional change intended. > > Signed-off-by: Mostafa Saleh > --- > Changes in v3: > -Add record_faults for stage-2 > -Reorder and document fields in SMMUTransCfg based on stage > -Rename oas in SMMUS2Cfg to eff_ps > -Improve comments in SMMUS2Cfg > Changes in v2: > -Add oas > --- > include/hw/arm/smmu-common.h | 22 +++++++++++++++++++--- > 1 file changed, 19 insertions(+), 3 deletions(-) > > diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h > index 9fcff26357..9cf3f37929 100644 > --- a/include/hw/arm/smmu-common.h > +++ b/include/hw/arm/smmu-common.h > @@ -58,25 +58,41 @@ typedef struct SMMUTLBEntry { > uint8_t granule; > } SMMUTLBEntry; > > +/* Stage-2 configuration. */ > +typedef struct SMMUS2Cfg { > + uint8_t tsz; /* Size of IPA input region (S2T0SZ) */ > + uint8_t sl0; /* Start level of translation (S2SL0) */ > + bool affd; /* AF Fault Disable (S2AFFD) */ > + bool record_faults; /* Record fault events (S2R) */ > + uint8_t granule_sz; /* Granule page shift (based on S2TG) */ > + uint8_t eff_ps; /* Effective PA output range (based on S2PS) */ > + uint16_t vmid; /* Virtual Machine ID (S2VMID) */ > + uint64_t vttb; /* Address of translation table base (S2TTB) */ > +} SMMUS2Cfg; > + > /* > * Generic structure populated by derived SMMU devices > * after decoding the configuration information and used as > * input to the page table walk > */ > typedef struct SMMUTransCfg { > + /* Shared fields between stage-1 and stage-2. */ > int stage; /* translation stage */ > - bool aa64; /* arch64 or aarch32 translation table */ > bool disabled; /* smmu is disabled */ > bool bypassed; /* translation is bypassed */ > bool aborted; /* translation is aborted */ > + uint32_t iotlb_hits; /* counts IOTLB hits */ > + uint32_t iotlb_misses; /* counts IOTLB misses*/ > + /* Used by stage-1 only. */ > + bool aa64; /* arch64 or aarch32 translation table */ > bool record_faults; /* record fault events */ > uint64_t ttb; /* TT base address */ > uint8_t oas; /* output address width */ > uint8_t tbi; /* Top Byte Ignore */ > uint16_t asid; > SMMUTransTableInfo tt[2]; > - uint32_t iotlb_hits; /* counts IOTLB hits for this asid */ > - uint32_t iotlb_misses; /* counts IOTLB misses for this asid */ > + /* Used by stage-2 only. */ > + struct SMMUS2Cfg s2cfg; > } SMMUTransCfg; > > typedef struct SMMUDevice { Reviewed-by: Eric Auger Thanks Eric