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[176.184.17.196]) by smtp.gmail.com with ESMTPSA id z11-20020a05600c0a0b00b0040d4e1393dcsm11616328wmp.20.2024.01.28.08.45.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 28 Jan 2024 08:45:08 -0800 (PST) Message-ID: <7d1fe607-0400-4308-b704-33481be2edc6@linaro.org> Date: Sun, 28 Jan 2024 17:45:06 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 07/33] target: Uninline cpu_mmu_index() Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: Anton Johansson References: <20240128044213.316480-1-richard.henderson@linaro.org> <20240128044213.316480-8-richard.henderson@linaro.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 28/1/24 17:41, Philippe Mathieu-Daudé wrote: > On 28/1/24 05:41, Richard Henderson wrote: >> From: Anton Johansson >> >> Uninlines the target-defined cpu_mmu_index() function by moving its >> definition to target/*/cpu.c.  This allows for compiling memory access >> functions in accel/tcg/cputlb.c without having to know target specifics. >> >> Signed-off-by: Anton Johansson >> Message-Id: <20240119144024.14289-13-anjo@rev.ng> >> Reviewed-by: Richard Henderson >> Signed-off-by: Richard Henderson >> --- >>   include/exec/cpu-common.h | 10 ++++++++++ >>   target/alpha/cpu.h        |  9 --------- >>   target/arm/cpu.h          | 13 ------------- >>   target/avr/cpu.h          |  7 ------- >>   target/cris/cpu.h         |  4 ---- >>   target/hexagon/cpu.h      |  9 --------- >>   target/hppa/cpu.h         | 13 ------------- >>   target/i386/cpu.h         |  7 ------- >>   target/loongarch/cpu.h    | 12 ------------ >>   target/m68k/cpu.h         |  4 ---- >>   target/microblaze/cpu.h   | 15 --------------- >>   target/mips/cpu.h         |  5 ----- >>   target/nios2/cpu.h        |  6 ------ >>   target/openrisc/cpu.h     | 12 ------------ >>   target/ppc/cpu.h          |  8 -------- >>   target/riscv/cpu.h        |  3 --- >>   target/rx/cpu.h           |  5 ----- >>   target/s390x/cpu.h        | 31 ------------------------------- >>   target/sh4/cpu.h          | 10 ---------- >>   target/sparc/cpu.h        | 28 ---------------------------- >>   target/tricore/cpu.h      |  5 ----- >>   target/xtensa/cpu.h       |  5 ----- >>   target/alpha/cpu.c        |  8 ++++++++ >>   target/arm/cpu.c          |  5 +++++ >>   target/avr/cpu.c          |  5 +++++ >>   target/cris/cpu.c         |  4 ++++ >>   target/hexagon/cpu.c      |  9 +++++++++ >>   target/hppa/cpu.c         | 13 +++++++++++++ >>   target/i386/cpu.c         |  7 +++++++ >>   target/loongarch/cpu.c    | 12 ++++++++++++ >>   target/m68k/cpu.c         |  5 +++++ >>   target/microblaze/cpu.c   | 16 ++++++++++++++++ >>   target/mips/cpu.c         |  5 +++++ >>   target/nios2/cpu.c        |  6 ++++++ >>   target/openrisc/cpu.c     | 12 ++++++++++++ >>   target/ppc/cpu.c          |  9 +++++++++ >>   target/riscv/cpu_helper.c |  2 +- >>   target/rx/cpu.c           |  5 +++++ >>   target/s390x/cpu.c        | 31 +++++++++++++++++++++++++++++++ >>   target/sh4/cpu.c          | 13 +++++++++++++ >>   target/sparc/cpu.c        | 28 ++++++++++++++++++++++++++++ >>   target/tricore/cpu.c      |  5 +++++ >>   target/xtensa/cpu.c       |  4 ++++ >>   43 files changed, 213 insertions(+), 212 deletions(-) >> >> diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h >> index 3109c6b67d..4724135f30 100644 >> --- a/include/exec/cpu-common.h >> +++ b/include/exec/cpu-common.h >> @@ -34,6 +34,16 @@ void cpu_list_lock(void); >>   void cpu_list_unlock(void); >>   unsigned int cpu_list_generation_id_get(void); >> +/** >> + * cpu_mmu_index: >> + * @env: The cpu environment >> + * @ifetch: True for code access, false for data access. >> + * >> + * Return the core mmu index for the current translation regime. >> + * This function is used by generic TCG code paths. >> + */ >> +int cpu_mmu_index(CPUArchState *env, bool ifetch); >> + >>   void tcg_iommu_init_notifier_list(CPUState *cpu); >>   void tcg_iommu_free_notifier_list(CPUState *cpu); > > I'm kind of reluctant to use CPUArchState in a -common.h header > (except in include/hw/core/cpu.h::cpu_env). > > Last Wednesday community call I mentioned to Anton I have a branch > going in the same direction he is taking, and suggested him to wait > to compare and unify our works. My bad I suppose, I should have replied to Anton series cover to update you about the plan discussed during that call. Also, if "This allows for compiling memory access functions in accel/tcg/cputlb.c without having to know target specifics." I'd rather see the corresponding meson change in the same patch.