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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd7f081sm1219571f8f.58.2025.02.06.01.19.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Feb 2025 01:19:41 -0800 (PST) Message-ID: <7d50d81c-982f-45f0-81eb-1c842b3c55cc@linaro.org> Date: Thu, 6 Feb 2025 10:19:40 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 09/17] hw/misc: Support 8-bytes memop in NPCM GCR module To: Hao Wu , peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, venture@google.com, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, hskinnemoen@google.com, titusr@google.com, chli30@nuvoton.corp-partner.google.com References: <20250206013105.3228344-1-wuhaotsh@google.com> <20250206013105.3228344-10-wuhaotsh@google.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250206013105.3228344-10-wuhaotsh@google.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/2/25 02:30, Hao Wu wrote: > The NPCM8xx GCR device can be accessed with 64-bit memory operations. > This patch supports that. > > Reviewed-by: Peter Maydell > Signed-off-by: Hao Wu > --- > hw/misc/npcm_gcr.c | 94 +++++++++++++++++++++++++++++++++----------- > hw/misc/trace-events | 4 +- > 2 files changed, 74 insertions(+), 24 deletions(-) > > diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c > index 820b730606..654e048048 100644 > --- a/hw/misc/npcm_gcr.c > +++ b/hw/misc/npcm_gcr.c > @@ -201,6 +201,7 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size) > uint32_t reg = offset / sizeof(uint32_t); > NPCMGCRState *s = opaque; > NPCMGCRClass *c = NPCM_GCR_GET_CLASS(s); > + uint64_t value; > > if (reg >= c->nr_regs) { > qemu_log_mask(LOG_GUEST_ERROR, > @@ -209,9 +210,21 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size) > return 0; > } > > - trace_npcm_gcr_read(offset, s->regs[reg]); > + switch (size) { > + case 4: > + value = s->regs[reg]; > + break; > + > + case 8: Should we assert(!(reg & 1)) in case someone want to enable unaligned accesses? > + value = deposit64(s->regs[reg], 32, 32, s->regs[reg + 1]); > + break; > + > + default: > + g_assert_not_reached(); > + } > > - return s->regs[reg]; > + trace_npcm_gcr_read(offset, value); > + return value; > } > > static void npcm_gcr_write(void *opaque, hwaddr offset, > @@ -231,29 +244,65 @@ static void npcm_gcr_write(void *opaque, hwaddr offset, > return; > } > > - switch (reg) { > - case NPCM7XX_GCR_PDID: > - case NPCM7XX_GCR_PWRON: > - case NPCM7XX_GCR_INTSR: > - qemu_log_mask(LOG_GUEST_ERROR, > - "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", > - __func__, offset); > - return; > - > - case NPCM7XX_GCR_RESSR: > - case NPCM7XX_GCR_CP2BST: > - /* Write 1 to clear */ > - value = s->regs[reg] & ~value; > + switch (size) { > + case 4: > + switch (reg) { > + case NPCM7XX_GCR_PDID: > + case NPCM7XX_GCR_PWRON: > + case NPCM7XX_GCR_INTSR: > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", > + __func__, offset); > + return; > + > + case NPCM7XX_GCR_RESSR: > + case NPCM7XX_GCR_CP2BST: > + /* Write 1 to clear */ > + value = s->regs[reg] & ~value; > + break; > + > + case NPCM7XX_GCR_RLOCKR1: > + case NPCM7XX_GCR_MDLR: > + /* Write 1 to set */ > + value |= s->regs[reg]; > + break; > + }; > + s->regs[reg] = value; > break; > > - case NPCM7XX_GCR_RLOCKR1: > - case NPCM7XX_GCR_MDLR: > - /* Write 1 to set */ > - value |= s->regs[reg]; > + case 8: Ditto. > + s->regs[reg] = value; > + s->regs[reg + 1] = extract64(v, 32, 32); > break; > - }; > > - s->regs[reg] = value; > + default: > + g_assert_not_reached(); > + } > +} > + > +static bool npcm_gcr_check_mem_op(void *opaque, hwaddr offset, > + unsigned size, bool is_write, > + MemTxAttrs attrs) > +{ > + NPCMGCRClass *c = NPCM_GCR_GET_CLASS(opaque); > + > + if (offset >= c->nr_regs * sizeof(uint32_t)) { > + return false; > + } > + > + switch (size) { > + case 4: > + return true; > + case 8: > + if (offset >= NPCM8XX_GCR_SCRPAD_00 * sizeof(uint32_t) && > + offset < (NPCM8XX_GCR_NR_REGS - 1) * sizeof(uint32_t)) { > + return true; > + } else { > + return false; > + } > + default: > + return false; > + } > } > > static const struct MemoryRegionOps npcm_gcr_ops = { > @@ -262,7 +311,8 @@ static const struct MemoryRegionOps npcm_gcr_ops = { > .endianness = DEVICE_LITTLE_ENDIAN, > .valid = { > .min_access_size = 4, > - .max_access_size = 4, > + .max_access_size = 8, > + .accepts = npcm_gcr_check_mem_op, > .unaligned = false, > }, > }; > diff --git a/hw/misc/trace-events b/hw/misc/trace-events > index 0f7204a237..f25dbd6030 100644 > --- a/hw/misc/trace-events > +++ b/hw/misc/trace-events > @@ -135,8 +135,8 @@ npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " valu > npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 > > # npcm_gcr.c > -npcm_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 > -npcm_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 > +npcm_gcr_read(uint64_t offset, uint64_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx64 > +npcm_gcr_write(uint64_t offset, uint64_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx64 > > # npcm7xx_mft.c > npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16