From: Laurent Vivier <laurent@vivier.eu>
To: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, qemu-devel@nongnu.org
Subject: Re: [PATCH v2 3/8] q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs
Date: Wed, 20 Oct 2021 16:04:07 +0200 [thread overview]
Message-ID: <7d9165eb-1001-6000-779c-a479cbc99279@vivier.eu> (raw)
In-Reply-To: <20211020134131.4392-4-mark.cave-ayland@ilande.co.uk>
Le 20/10/2021 à 15:41, Mark Cave-Ayland a écrit :
> In order to allow dynamic routing of IRQs to different IRQ levels on the CPU
> depending upon port B bit 6, use GLUE IRQ numbers and map them to the the
> corresponding CPU IRQ level accordingly.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 32 ++++++++++++++++++++++++++++----
> 1 file changed, 28 insertions(+), 4 deletions(-)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index 15f3067811..81c335bf16 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -102,11 +102,34 @@ struct GLUEState {
> uint8_t ipr;
> };
>
> +#define GLUE_IRQ_IN_VIA1 0
> +#define GLUE_IRQ_IN_VIA2 1
> +#define GLUE_IRQ_IN_SONIC 2
> +#define GLUE_IRQ_IN_ESCC 3
> +
> static void GLUE_set_irq(void *opaque, int irq, int level)
> {
> GLUEState *s = opaque;
> int i;
>
> + switch (irq) {
> + case GLUE_IRQ_IN_VIA1:
> + irq = 5;
> + break;
> +
> + case GLUE_IRQ_IN_VIA2:
> + irq = 1;
> + break;
> +
> + case GLUE_IRQ_IN_SONIC:
> + irq = 2;
> + break;
> +
> + case GLUE_IRQ_IN_ESCC:
> + irq = 3;
> + break;
> + }
> +
> if (level) {
> s->ipr |= 1 << irq;
> } else {
> @@ -284,7 +307,7 @@ static void q800_init(MachineState *machine)
> sysbus = SYS_BUS_DEVICE(via1_dev);
> sysbus_realize_and_unref(sysbus, &error_fatal);
> sysbus_mmio_map(sysbus, 1, VIA_BASE);
> - sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, 5));
> + sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA1));
>
> adb_bus = qdev_get_child_bus(via1_dev, "adb.0");
> dev = qdev_new(TYPE_ADB_KEYBOARD);
> @@ -297,7 +320,7 @@ static void q800_init(MachineState *machine)
> sysbus = SYS_BUS_DEVICE(via2_dev);
> sysbus_realize_and_unref(sysbus, &error_fatal);
> sysbus_mmio_map(sysbus, 1, VIA_BASE + VIA_SIZE);
> - sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, 1));
> + sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA2));
>
> /* MACSONIC */
>
> @@ -330,7 +353,7 @@ static void q800_init(MachineState *machine)
> sysbus = SYS_BUS_DEVICE(dev);
> sysbus_realize_and_unref(sysbus, &error_fatal);
> sysbus_mmio_map(sysbus, 0, SONIC_BASE);
> - sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, 2));
> + sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_SONIC));
>
> memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-q800.prom",
> SONIC_PROM_SIZE, &error_fatal);
> @@ -366,7 +389,8 @@ static void q800_init(MachineState *machine)
> qdev_realize_and_unref(escc_orgate, NULL, &error_fatal);
> sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(escc_orgate, 0));
> sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(escc_orgate, 1));
> - qdev_connect_gpio_out(DEVICE(escc_orgate), 0, qdev_get_gpio_in(glue, 3));
> + qdev_connect_gpio_out(DEVICE(escc_orgate), 0,
> + qdev_get_gpio_in(glue, GLUE_IRQ_IN_ESCC));
> sysbus_mmio_map(sysbus, 0, SCC_BASE);
>
> /* SCSI */
>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
next prev parent reply other threads:[~2021-10-20 14:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-20 13:41 [PATCH v2 0/8] q800: GLUE updates for A/UX mode Mark Cave-Ayland
2021-10-20 13:41 ` [PATCH v2 1/8] mac_via: update comment for VIA1B_vMystery bit Mark Cave-Ayland
2021-10-20 13:41 ` [PATCH v2 2/8] q800: move VIA1 IRQ from level 1 to level 6 Mark Cave-Ayland
2021-10-20 13:41 ` [PATCH v2 3/8] q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs Mark Cave-Ayland
2021-10-20 14:04 ` Laurent Vivier [this message]
2021-10-20 13:41 ` [PATCH v2 4/8] mac_via: add GPIO for A/UX mode Mark Cave-Ayland
2021-10-20 13:41 ` [PATCH v2 5/8] q800: wire up auxmode GPIO to GLUE Mark Cave-Ayland
2021-10-20 13:41 ` [PATCH v2 6/8] q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic mode Mark Cave-Ayland
2021-10-20 14:07 ` Laurent Vivier
2021-10-20 13:41 ` [PATCH v2 7/8] q800: wire up remaining IRQs " Mark Cave-Ayland
2021-10-20 13:41 ` [PATCH v2 8/8] q800: add NMI handler Mark Cave-Ayland
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