Re: [PATCH 1/1] accel/tcg: Fix computing is_write for mips

[Richard Henderson <richard.henderson@linaro.org>]

On 9/10/20 12:43 AM, Kele Huang wrote:
> Detect mips store instructions SWXC1 and SDXC1 for MIPS64 since
> MIPS64r1, and MIPS32 since MIPS32r2.
> 
> Signed-off-by: Kele Huang <kele.hwang@gmail.com>
> ---
>  accel/tcg/user-exec.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index bb039eb32d..e69b4d8780 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -712,6 +712,27 @@ int cpu_signal_handler(int host_signum, void *pinfo,
>  
>      /* XXX: compute is_write */
>      is_write = 0;
> +
> +    /*
> +     * Detect store instructions. Required in all versions of MIPS64
> +     * since MIPS64r1. Not available in MIPS32r1. Required by MIPS32r2
> +     * and subsequent versions of MIPS32.
> +     */
> +    switch ((insn >> 3) & 0x7) {
> +        case 0x1:
> +            switch (insn & 0x7) {
> +            case 0x0: /* SWXC1 */
> +            case 0x1: /* SDXC1 */
> +                is_write = 1;
> +                break;
> +            default:
> +                break;
> +            }
> +            break;
> +        default:
> +            break;


You should detect all of the store instructions, not just the coprocessor ones.
 Compare, for example, the Sparc version around line 485.

Once done, you can also remove that /* XXX */ comment just above, which
indicates that there is work that needs doing.


r~