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[2.142.241.104]) by smtp.gmail.com with ESMTPSA id r8sm27879525wrz.43.2021.11.10.02.52.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Nov 2021 02:52:32 -0800 (PST) Subject: Re: [PATCH v2 05/14] target/riscv: Calculate address according to XLEN To: LIU Zhiwei , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alexey Baturo References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> <20211110070452.48539-6-zhiwei_liu@c-sky.com> From: Richard Henderson Message-ID: <7dace3b5-1320-20b3-703c-bbdf7e745fb9@linaro.org> Date: Wed, 10 Nov 2021 11:52:29 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211110070452.48539-6-zhiwei_liu@c-sky.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::332 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.678, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/10/21 8:04 AM, LIU Zhiwei wrote: > Signed-off-by: LIU Zhiwei > --- > target/riscv/insn_trans/trans_rvd.c.inc | 23 ++--------------------- > target/riscv/insn_trans/trans_rvf.c.inc | 23 ++--------------------- > target/riscv/insn_trans/trans_rvi.c.inc | 18 ++---------------- > target/riscv/translate.c | 13 +++++++++++++ > 4 files changed, 19 insertions(+), 58 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc > index 64fb0046f7..29066a8ef3 100644 > --- a/target/riscv/insn_trans/trans_rvd.c.inc > +++ b/target/riscv/insn_trans/trans_rvd.c.inc > @@ -20,19 +20,10 @@ > > static bool trans_fld(DisasContext *ctx, arg_fld *a) > { > - TCGv addr; > - > + TCGv addr = get_address(ctx, a->rs1, a->imm); > REQUIRE_FPU; > REQUIRE_EXT(ctx, RVD); It would be better to leave the address calculation after the REQUIRE checks. > +static TCGv get_address(DisasContext *ctx, int rs1, int imm) > +{ > + TCGv addr = temp_new(ctx); > + TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); > + > + tcg_gen_addi_tl(addr, src1, imm); > + addr = gen_pm_adjust_address(ctx, addr); > + if (get_xl(ctx) == MXL_RV32) { > + tcg_gen_ext32u_tl(addr, addr); > + } > + return addr; > +} I suspect the extend should come before the pointer mask and not after, but this is is a weakness in the current RVJ spec that it does not specify how the extension interacts with UXL. (The reverse ordering would allow a 64-bit os to place a 32-bit application at a base address above 4gb, which could allow address separation without paging enabled.) I do think we should merge gen_pm_adjust_address into this function so that we only create one new temporary. r~