From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, LIU Zhiwei <lzw194868@alibaba-inc.com>
Subject: Re: [PATCH] qemu/timer: Add host ticks function for RISC-V
Date: Sat, 9 Sep 2023 10:43:21 -0700 [thread overview]
Message-ID: <7dcb92db-b3c6-7236-cccd-fb6dc9d388a9@linaro.org> (raw)
In-Reply-To: <20230908032300.646-1-zhiwei_liu@linux.alibaba.com>
On 9/7/23 20:23, LIU Zhiwei wrote:
> From: LIU Zhiwei <lzw194868@alibaba-inc.com>
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
> include/qemu/timer.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/include/qemu/timer.h b/include/qemu/timer.h
> index 9a91cb1248..ce0b66d122 100644
> --- a/include/qemu/timer.h
> +++ b/include/qemu/timer.h
> @@ -979,6 +979,25 @@ static inline int64_t cpu_get_host_ticks(void)
> return cur - ofs;
> }
>
> +#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 32
> +static inline int64_t cpu_get_host_ticks(void)
> +{
> + uint32_t lo, hi;
> + asm volatile("RDCYCLE %0\n\t"
> + "RDCYCLEH %1"
> + : "=r"(lo), "=r"(hi));
> + return lo | (uint64_t)hi << 32;
> +}
> +
> +#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen > 32
> +static inline int64_t cpu_get_host_ticks(void)
> +{
> + int64_t val;
> +
> + asm volatile("RDCYCLE %0" : "=r"(cc));
> + return val;
> +}
__riscv_xlen should never be undefined.
Don't you need a loop for RDCYCLEH to avoid time going backward?
do {
asm("rdcycleh %0\n\t"
"rdcycle %1\n\t"
"rdcycleh %2\n\t"
: "=r"(hi), "=r"(lo), "=r"(tmph));
} while (unlikely(tmph != hi));
r~
next prev parent reply other threads:[~2023-09-09 17:44 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-08 3:23 [PATCH] qemu/timer: Add host ticks function for RISC-V LIU Zhiwei
2023-09-09 17:43 ` Richard Henderson [this message]
2023-09-11 5:53 ` LIU Zhiwei
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