From: Richard Henderson <richard.henderson@linaro.org>
To: Deepak Gupta <debug@rivosinc.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
andy.chiu@sifive.com, kito.cheng@sifive.com
Subject: Re: [PATCH v12 01/20] target/riscv: expose *envcfg csr and priv to qemu-user as well
Date: Fri, 30 Aug 2024 12:10:29 +1000 [thread overview]
Message-ID: <7e4ee645-41ba-4a6b-a004-df396faff65b@linaro.org> (raw)
In-Reply-To: <20240829233425.1005029-2-debug@rivosinc.com>
On 8/30/24 09:34, Deepak Gupta wrote:
> Execution environment config CSR controlling user env and current
> privilege state shouldn't be limited to qemu-system only. *envcfg
> CSRs control enabling of features in next lesser mode. In some cases
> bits *envcfg CSR can be lit up by kernel as part of kernel policy or
> software (user app) can choose to opt-in by issuing a system call
> (e.g. prctl). In case of qemu-user, it should be no different because
> qemu is providing underlying execution environment facility and thus
> either should provide some default value in *envcfg CSRs or react to
> system calls (prctls) initiated from application. priv is set to PRV_U
> and menvcfg/senvcfg set to 0 for qemu-user on reest.
>
> `henvcfg` has been left for qemu-system only because it is not expected
> that someone will use qemu-user where application is expected to have
> hypervisor underneath which is controlling its execution environment. If
> such a need arises then `henvcfg` could be exposed as well.
>
> Relevant discussion:
> https://lore.kernel.org/all/
> CAKmqyKOTVWPFep2msTQVdUmJErkH+bqCcKEQ4hAnyDFPdWKe0Q@mail.gmail.com/
>
> Signed-off-by: Deepak Gupta<debug@rivosinc.com>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis<alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 5 +++++
> target/riscv/cpu.h | 9 +++++----
> 2 files changed, 10 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2024-08-30 2:11 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-29 23:34 [PATCH v12 00/20] riscv support for control flow integrity extensions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 01/20] target/riscv: expose *envcfg csr and priv to qemu-user as well Deepak Gupta
2024-08-30 2:10 ` Richard Henderson [this message]
2024-08-29 23:34 ` [PATCH v12 02/20] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 04/20] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-30 2:13 ` Richard Henderson
2024-08-29 23:34 ` [PATCH v12 05/20] target/riscv: additional code information for sw check Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 07/20] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 08/20] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 09/20] target/riscv: Expose zicfilp extension as a cpu property Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 10/20] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 11/20] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-30 5:20 ` Richard Henderson
2024-08-30 5:56 ` Deepak Gupta
2024-08-30 16:30 ` Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 12/20] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 13/20] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 14/20] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 15/20] target/riscv: update `decode_save_opc` to store extra word2 Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 16/20] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 17/20] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 18/20] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 19/20] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 20/20] target/riscv: Expose zicfiss extension as a cpu property Deepak Gupta
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