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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Zhao Liu <zhao1.liu@linux.intel.com>,
	Eduardo Habkost <eduardo@habkost.net>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
	Yanan Wang <wangyanan55@huawei.com>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Eric Blake <eblake@redhat.com>,
	Markus Armbruster <armbru@redhat.com>,
	Marcelo Tosatti <mtosatti@redhat.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
	Babu Moger <babu.moger@amd.com>,
	Xiaoyao Li <xiaoyao.li@intel.com>,
	Zhenyu Wang <zhenyu.z.wang@intel.com>,
	Zhuocheng Ding <zhuocheng.ding@intel.com>,
	Yongwei Ma <yongwei.ma@intel.com>, Zhao Liu <zhao1.liu@intel.com>
Subject: Re: [PATCH v8 10/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB]
Date: Wed, 7 Feb 2024 07:00:50 +0100	[thread overview]
Message-ID: <7ebf479e-271f-42a8-8df0-f124dc481dca@linaro.org> (raw)
In-Reply-To: <20240131101350.109512-11-zhao1.liu@linux.intel.com>

On 31/1/24 11:13, Zhao Liu wrote:
> From: Zhao Liu <zhao1.liu@intel.com>
> 
> CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared
> by Intel and AMD CPUs.
> 
> But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU
> (in CPUID[0x80000026]) have the different definitions with different
> enumeration values.
> 
> Though CPUID[0x80000026] hasn't been implemented in QEMU, to avoid
> possible misunderstanding, split topology types of CPUID[0x1F] from the
> definitions of CPUID[0xB] and introduce CPUID[0x1F]-specific topology
> types.
> 
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> Tested-by: Babu Moger <babu.moger@amd.com>
> Tested-by: Yongwei Ma <yongwei.ma@intel.com>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> Changes since v3:
>   * New commit to prepare to refactor CPUID[0x1F] encoding.
> ---
>   target/i386/cpu.c | 14 +++++++-------
>   target/i386/cpu.h | 13 +++++++++----
>   2 files changed, 16 insertions(+), 11 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>



  reply	other threads:[~2024-02-07  6:01 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-31 10:13 [PATCH v8 00/21] Introduce smp.modules for x86 in QEMU Zhao Liu
2024-01-31 10:13 ` [PATCH v8 01/21] hw/core/machine: Introduce the module as a CPU topology level Zhao Liu
2024-01-31 10:13 ` [PATCH v8 02/21] hw/core/machine: Support modules in -smp Zhao Liu
2024-01-31 10:13 ` [PATCH v8 03/21] hw/core: Introduce module-id as the topology subindex Zhao Liu
2024-01-31 10:13 ` [PATCH v8 04/21] hw/core: Support module-id in numa configuration Zhao Liu
2024-01-31 10:13 ` [PATCH v8 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Zhao Liu
2024-01-31 10:13 ` [PATCH v8 06/21] i386/cpu: Use APIC ID info to encode cache topo in CPUID[4] Zhao Liu
2024-01-31 10:13 ` [PATCH v8 07/21] i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2024-01-31 10:13 ` [PATCH v8 08/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Zhao Liu
2024-02-07  5:59   ` Philippe Mathieu-Daudé
2024-01-31 10:13 ` [PATCH v8 09/21] i386/cpu: Introduce bitmap to cache available CPU topology levels Zhao Liu
2024-01-31 10:13 ` [PATCH v8 10/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Zhao Liu
2024-02-07  6:00   ` Philippe Mathieu-Daudé [this message]
2024-01-31 10:13 ` [PATCH v8 11/21] i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology level Zhao Liu
2024-01-31 10:13 ` [PATCH v8 12/21] i386: Introduce module level cpu topology to CPUX86State Zhao Liu
2024-01-31 10:13 ` [PATCH v8 13/21] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2024-01-31 10:13 ` [PATCH v8 14/21] i386: Expose module level in CPUID[0x1F] Zhao Liu
2024-01-31 10:13 ` [PATCH v8 15/21] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2024-01-31 10:13 ` [PATCH v8 16/21] i386/cpu: Introduce module-id to X86CPU Zhao Liu
2024-01-31 10:13 ` [PATCH v8 17/21] tests: Add test case of APIC ID for module level parsing Zhao Liu
2024-01-31 10:13 ` [PATCH v8 18/21] hw/i386/pc: Support smp.modules for x86 PC machine Zhao Liu
2024-01-31 10:13 ` [PATCH v8 19/21] i386: Add cache topology info in CPUCacheInfo Zhao Liu
2024-01-31 10:13 ` [PATCH v8 20/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[4] Zhao Liu
2024-01-31 10:13 ` [PATCH v8 21/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2024-01-31 10:28 ` [PATCH v8 00/21] Introduce smp.modules for x86 in QEMU Daniel P. Berrangé
2024-02-01  2:57   ` Zhao Liu
2024-02-01  9:21     ` Daniel P. Berrangé
2024-02-01 16:10       ` Zhao Liu
2024-02-08 16:52         ` Daniel P. Berrangé
2024-02-15 16:56           ` Zhao Liu
2024-02-21 12:41 ` Markus Armbruster
2024-02-21 15:15   ` Zhao Liu

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