From: LIU Zhiwei <baxiantai@gmail.com>
To: Christoph Muellner <christoph.muellner@vrull.eu>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Richard Henderson <richard.henderson@linaro.org>,
Zhiwei Liu <zhiwei_liu@linux.alibaba.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: Weiwei Li <liweiwei@iscas.ac.cn>
Subject: Re: [PATCH v2 2/8] target/riscv: Factor out extension tests to cpu_cfg.h
Date: Mon, 12 Jun 2023 19:58:20 +0800 [thread overview]
Message-ID: <7f1545ff-3896-4dee-b96a-72f417a5c339@gmail.com> (raw)
In-Reply-To: <20230612111034.3955227-3-christoph.muellner@vrull.eu>
On 2023/6/12 19:10, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This patch moves the extension test functions that are used
> to gate vendor extension decoders, into cpu_cfg.h.
> This allows to reuse them in the disassembler.
>
> This patch does not introduce new functionality.
> However, the patch includes a small change:
> The parameter for the extension test functions has been changed
> from 'DisasContext*' to 'const RISCVCPUConfig*' to keep
> the code in cpu_cfg.h self-contained.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> ---
> target/riscv/cpu_cfg.h | 26 ++++++++++++++++++++++++++
> target/riscv/translate.c | 27 ++-------------------------
> 2 files changed, 28 insertions(+), 25 deletions(-)
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index c4a627d335..0b4fe4b540 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -133,4 +133,30 @@ struct RISCVCPUConfig {
> };
>
> typedef struct RISCVCPUConfig RISCVCPUConfig;
> +
> +/* Helper functions to test for extensions. */
> +
> +static inline bool always_true_p(const RISCVCPUConfig *cfg __attribute__((__unused__)))
> +{
> + return true;
> +}
> +
> +static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
> +{
> + return cfg->ext_xtheadba || cfg->ext_xtheadbb ||
> + cfg->ext_xtheadbs || cfg->ext_xtheadcmo ||
> + cfg->ext_xtheadcondmov ||
> + cfg->ext_xtheadfmemidx || cfg->ext_xtheadfmv ||
> + cfg->ext_xtheadmac || cfg->ext_xtheadmemidx ||
> + cfg->ext_xtheadmempair || cfg->ext_xtheadsync;
> +}
> +
> +#define MATERIALISE_EXT_PREDICATE(ext) \
> + static inline bool has_ ## ext ## _p(const RISCVCPUConfig *cfg) \
> + { \
> + return cfg->ext_ ## ext ; \
> + }
> +
> +MATERIALISE_EXT_PREDICATE(XVentanaCondOps)
> +
> #endif
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 859d5b2dcf..275b922811 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -119,29 +119,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> return ctx->misa_ext & ext;
> }
>
> -static bool always_true_p(DisasContext *ctx __attribute__((__unused__)))
> -{
> - return true;
> -}
> -
> -static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
> -{
> - return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
> - ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
> - ctx->cfg_ptr->ext_xtheadcondmov ||
> - ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv ||
> - ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx ||
> - ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync;
> -}
> -
> -#define MATERIALISE_EXT_PREDICATE(ext) \
> - static bool has_ ## ext ## _p(DisasContext *ctx) \
> - { \
> - return ctx->cfg_ptr->ext_ ## ext ; \
> - }
> -
> -MATERIALISE_EXT_PREDICATE(XVentanaCondOps);
> -
> #ifdef TARGET_RISCV32
> #define get_xl(ctx) MXL_RV32
> #elif defined(CONFIG_USER_ONLY)
> @@ -1132,7 +1109,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
> * that are tested in-order until a decoder matches onto the opcode.
> */
> static const struct {
> - bool (*guard_func)(DisasContext *);
> + bool (*guard_func)(const RISCVCPUConfig *);
> bool (*decode_func)(DisasContext *, uint32_t);
> } decoders[] = {
> { always_true_p, decode_insn32 },
> @@ -1161,7 +1138,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
> ctx->opcode = opcode32;
>
> for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
> - if (decoders[i].guard_func(ctx) &&
> + if (decoders[i].guard_func(ctx->cfg_ptr) &&
> decoders[i].decode_func(ctx, opcode32)) {
> return;
> }
next prev parent reply other threads:[~2023-06-12 11:59 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-12 11:10 [PATCH v2 0/8] disas/riscv: Add vendor extension support Christoph Muellner
2023-06-12 11:10 ` [PATCH v2 1/8] target/riscv: Use xl instead of mxl for disassemble Christoph Muellner
2023-06-12 11:10 ` [PATCH v2 2/8] target/riscv: Factor out extension tests to cpu_cfg.h Christoph Muellner
2023-06-12 11:58 ` LIU Zhiwei [this message]
2023-06-14 8:58 ` Daniel Henrique Barboza
2023-06-15 6:35 ` Weiwei Li
2023-06-12 11:10 ` [PATCH v2 3/8] disas/riscv: Move types/constants to new header file Christoph Muellner
2023-06-12 11:10 ` [PATCH v2 4/8] disas/riscv: Make rv_op_illegal a shared enum value Christoph Muellner
2023-06-12 11:10 ` [PATCH v2 5/8] disas/riscv: Encapsulate opcode_data into decode Christoph Muellner
2023-06-12 11:10 ` [PATCH v2 6/8] disas/riscv: Provide infrastructure for vendor extensions Christoph Muellner
2023-06-12 11:10 ` [PATCH v2 7/8] disas/riscv: Add support for XVentanaCondOps Christoph Muellner
2023-06-14 9:00 ` Daniel Henrique Barboza
2023-06-12 11:10 ` [PATCH v2 8/8] disas/riscv: Add support for XThead* instructions Christoph Muellner
2023-06-15 6:53 ` Weiwei Li
2023-06-26 8:02 ` Christoph Müllner
2023-06-22 1:03 ` [PATCH v2 0/8] disas/riscv: Add vendor extension support Alistair Francis
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