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Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v2 2/8] target/riscv: Factor out extension tests to cpu_cfg.h Content-Language: en-US To: Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Richard Henderson , Zhiwei Liu , Daniel Henrique Barboza Cc: Weiwei Li References: <20230612111034.3955227-1-christoph.muellner@vrull.eu> <20230612111034.3955227-3-christoph.muellner@vrull.eu> From: LIU Zhiwei In-Reply-To: <20230612111034.3955227-3-christoph.muellner@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=baxiantai@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.096, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2023/6/12 19:10, Christoph Muellner wrote: > From: Christoph Müllner > > This patch moves the extension test functions that are used > to gate vendor extension decoders, into cpu_cfg.h. > This allows to reuse them in the disassembler. > > This patch does not introduce new functionality. > However, the patch includes a small change: > The parameter for the extension test functions has been changed > from 'DisasContext*' to 'const RISCVCPUConfig*' to keep > the code in cpu_cfg.h self-contained. > > Signed-off-by: Christoph Müllner Reviewed-by: LIU Zhiwei Zhiwei > --- > target/riscv/cpu_cfg.h | 26 ++++++++++++++++++++++++++ > target/riscv/translate.c | 27 ++------------------------- > 2 files changed, 28 insertions(+), 25 deletions(-) > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index c4a627d335..0b4fe4b540 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -133,4 +133,30 @@ struct RISCVCPUConfig { > }; > > typedef struct RISCVCPUConfig RISCVCPUConfig; > + > +/* Helper functions to test for extensions. */ > + > +static inline bool always_true_p(const RISCVCPUConfig *cfg __attribute__((__unused__))) > +{ > + return true; > +} > + > +static inline bool has_xthead_p(const RISCVCPUConfig *cfg) > +{ > + return cfg->ext_xtheadba || cfg->ext_xtheadbb || > + cfg->ext_xtheadbs || cfg->ext_xtheadcmo || > + cfg->ext_xtheadcondmov || > + cfg->ext_xtheadfmemidx || cfg->ext_xtheadfmv || > + cfg->ext_xtheadmac || cfg->ext_xtheadmemidx || > + cfg->ext_xtheadmempair || cfg->ext_xtheadsync; > +} > + > +#define MATERIALISE_EXT_PREDICATE(ext) \ > + static inline bool has_ ## ext ## _p(const RISCVCPUConfig *cfg) \ > + { \ > + return cfg->ext_ ## ext ; \ > + } > + > +MATERIALISE_EXT_PREDICATE(XVentanaCondOps) > + > #endif > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 859d5b2dcf..275b922811 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -119,29 +119,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) > return ctx->misa_ext & ext; > } > > -static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) > -{ > - return true; > -} > - > -static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) > -{ > - return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || > - ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || > - ctx->cfg_ptr->ext_xtheadcondmov || > - ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || > - ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || > - ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; > -} > - > -#define MATERIALISE_EXT_PREDICATE(ext) \ > - static bool has_ ## ext ## _p(DisasContext *ctx) \ > - { \ > - return ctx->cfg_ptr->ext_ ## ext ; \ > - } > - > -MATERIALISE_EXT_PREDICATE(XVentanaCondOps); > - > #ifdef TARGET_RISCV32 > #define get_xl(ctx) MXL_RV32 > #elif defined(CONFIG_USER_ONLY) > @@ -1132,7 +1109,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) > * that are tested in-order until a decoder matches onto the opcode. > */ > static const struct { > - bool (*guard_func)(DisasContext *); > + bool (*guard_func)(const RISCVCPUConfig *); > bool (*decode_func)(DisasContext *, uint32_t); > } decoders[] = { > { always_true_p, decode_insn32 }, > @@ -1161,7 +1138,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) > ctx->opcode = opcode32; > > for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { > - if (decoders[i].guard_func(ctx) && > + if (decoders[i].guard_func(ctx->cfg_ptr) && > decoders[i].decode_func(ctx, opcode32)) { > return; > }