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Tsirkin" , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20230105143228.244965-1-shentey@gmail.com> <50FFD7E4-A40C-4428-ACD2-F7C93C687572@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <50FFD7E4-A40C-4428-ACD2-F7C93C687572@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/1/23 16:12, Bernhard Beschow wrote: > Am 7. Januar 2023 23:57:32 UTC schrieb Mark Cave-Ayland : >> On 05/01/2023 14:31, Bernhard Beschow wrote: >>> Bernhard Beschow (28): >>> hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig >>> hw/usb/hcd-uhci: Introduce TYPE_ defines for device models >>> hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is >>> created >>> hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 >>> south bridge >>> hw/i386/pc: Create RTC controllers in south bridges >>> hw/i386/pc: No need for rtc_state to be an out-parameter >>> hw/isa/piix3: Create USB controller in host device >>> hw/isa/piix3: Create power management controller in host device >>> hw/intc/i8259: Make using the isa_pic singleton more type-safe >>> hw/intc/i8259: Introduce i8259 proxy "isa-pic" >>> hw/isa/piix3: Create ISA PIC in host device >>> hw/isa/piix3: Create IDE controller in host device >>> hw/isa/piix3: Wire up ACPI interrupt internally >>> hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS >>> hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 >>> hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 >>> hw/isa/piix3: Drop the "3" from PIIX base class >>> hw/isa/piix4: Make PIIX4's ACPI and USB functions optional >>> hw/isa/piix4: Remove unused inbound ISA interrupt lines >>> hw/isa/piix4: Use ISA PIC device >>> hw/isa/piix4: Reuse struct PIIXState from PIIX3 >>> hw/isa/piix4: Rename reset control operations to match PIIX3 >>> hw/isa/piix3: Merge hw/isa/piix4.c >>> hw/isa/piix: Harmonize names of reset control memory regions >>> hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 >>> hw/isa/piix: Rename functions to be shared for interrupt triggering >>> hw/isa/piix: Consolidate IRQ triggering >>> hw/isa/piix: Share PIIX3's base class with PIIX4 >> Phil - over to you! Thanks for the review Mark! > Shall I respin? I could integrate my PCI series into this one in order to avoid the outdated MIPS patches while still delivering a working series. Yes/No? If you don't mind, that is certainly easier for me :)