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[174.21.71.127]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21c2d3ac93bsm1620295ad.157.2025.01.16.07.22.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Jan 2025 07:22:03 -0800 (PST) Message-ID: <7f645bf5-3d57-4803-a937-f8e558391e8d@linaro.org> Date: Thu, 16 Jan 2025 07:22:01 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] target/i386: Do not raise Invalid for 0 * Inf + QNaN To: Peter Maydell , qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?UTF-8?Q?Alex_Benn=C3=A9e?= References: <20250116112536.4117889-1-peter.maydell@linaro.org> <20250116112536.4117889-2-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250116112536.4117889-2-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/16/25 03:25, Peter Maydell wrote: > In commit 8adcff4ae7 ("fpu: handle raising Invalid for infzero in > pick_nan_muladd") we changed the handling of 0 * Inf + QNaN to always > raise the Invalid exception regardless of target architecture. (This > was a change affecting hppa, i386, sh4 and tricore.) However, this > was incorrect for i386, which documents in the SDM section 14.5.2 > that for the 0 * Inf + NaN case that it will only raise the Invalid > exception when the input is an SNaN. (This is permitted by the IEEE > 754-2008 specification, which documents that whether we raise Invalid > for 0 * Inf + QNaN is implementation defined.) > > Adjust the softfloat pick_nan_muladd code to allow the target to > suppress the raising of Invalid for the inf * zero + NaN case (as an > extra flag orthogonal to its choice for when to use the default NaN), > and enable that for x86. > > We do not revert here the behaviour change for hppa, sh4 or tricore: > * The sh4 manual is clear that it should signal Invalid > * The tricore manual is a bit vague but doesn't say it shouldn't > * The hppa manual doesn't talk about fused multiply-add corner > cases at all > > Cc: qemu-stable@nongnu.org > Fixes: 8adcff4ae7 (""fpu: handle raising Invalid for infzero in pick_nan_muladd") > Signed-off-by: Peter Maydell > --- > include/fpu/softfloat-types.h | 16 +++++++++++++--- > target/i386/tcg/fpu_helper.c | 5 ++++- > fpu/softfloat-parts.c.inc | 5 +++-- > 3 files changed, 20 insertions(+), 6 deletions(-) > > diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h > index 9d37cdfaa8e..c51b2a5b3de 100644 > --- a/include/fpu/softfloat-types.h > +++ b/include/fpu/softfloat-types.h > @@ -278,11 +278,21 @@ typedef enum __attribute__((__packed__)) { > /* No propagation rule specified */ > float_infzeronan_none = 0, > /* Result is never the default NaN (so always the input NaN) */ > - float_infzeronan_dnan_never, > + float_infzeronan_dnan_never = 1, > /* Result is always the default NaN */ > - float_infzeronan_dnan_always, > + float_infzeronan_dnan_always = 2, > /* Result is the default NaN if the input NaN is quiet */ > - float_infzeronan_dnan_if_qnan, > + float_infzeronan_dnan_if_qnan = 3, > + /* > + * Don't raise Invalid for 0 * Inf + NaN. Default is to raise. > + * IEEE 754-2008 section 7.2 makes it implementation defined whether > + * 0 * Inf + QNaN raises Invalid or not. Note that 0 * Inf + SNaN will > + * raise the Invalid flag for the SNaN anyway. > + * > + * This is a flag which can be ORed in with any of the above > + * DNaN behaviour options. > + */ > + float_infzeronan_suppress_invalid = (1 << 7), Why 128 and not 4? Otherwise, Reviewed-by: Richard Henderson r~