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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3d520eada16sm6050775f8f.41.2025.09.01.03.53.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Sep 2025 03:53:27 -0700 (PDT) Message-ID: <7f6fc4f0-9c83-4106-a408-dc213467c96c@linaro.org> Date: Mon, 1 Sep 2025 12:53:27 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 08/14] hw/misc: Add RISC-V CMGCR device implementation To: Djordje Todorovic , "qemu-devel@nongnu.org" Cc: "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" References: <20250717093833.402237-1-djordje.todorovic@htecgroup.com> <20250717093833.402237-9-djordje.todorovic@htecgroup.com> <1cf4f7e5-c9d2-49fd-98db-fd8d05fd241f@linaro.org> <4b7973d5-c126-44c8-970d-27059a806512@htecgroup.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <4b7973d5-c126-44c8-970d-27059a806512@htecgroup.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/9/25 10:24, Djordje Todorovic wrote: > > On 8. 8. 25. 18:07, Philippe Mathieu-Daudé wrote: >> CAUTION: This email originated from outside of the organization. Do >> not click links or open attachments unless you recognize the sender >> and know the content is safe. >> >> >> On 8/8/25 18:00, Philippe Mathieu-Daudé wrote: >>> On 17/7/25 11:38, Djordje Todorovic wrote: >>>> Add RISC-V implementation of the Coherent Manager Global Control >>>> Register (CMGCR) device. It is based on the existing MIPS CMGCR >>>> implementation but adapted for RISC-V systems. >>>> >>>> The CMGCR device provides global system control for multi-core >>>> configurations in RISC-V systems. >>>> >>>> This is needed for the MIPS BOSTON AIA board. >>>> >>>> Signed-off-by: Chao-ying Fu >>>> Signed-off-by: Djordje Todorovic >>>> --- >>>>   hw/misc/Kconfig               |  10 ++ >>>>   hw/misc/meson.build           |   2 + >>>>   hw/misc/riscv_cmgcr.c         | 234 >>>> ++++++++++++++++++++++++++++++++++ >>>>   include/hw/misc/riscv_cmgcr.h |  49 +++++++ >>>>   4 files changed, 295 insertions(+) >>>>   create mode 100644 hw/misc/riscv_cmgcr.c >>>>   create mode 100644 include/hw/misc/riscv_cmgcr.h >>> >>> >>>> +static void riscv_gcr_realize(DeviceState *dev, Error **errp) >>>> +{ >>>> +    RISCVGCRState *s = RISCV_GCR(dev); >>> >>> Please report an error for invalid num_vps values (0 or >MAX). >> >> Per the next patch: >> >>   #define VPS_MAX 64 >> >> Is it possible to have a config with 7, 24 or 35 vps? >> > 64 is maximum, and we can have fewer than 64 vps. > So, yes, it is possible to have that configuration. Please provide a test with 7 and 35 VPs then. Thanks!