Re: [PATCH 04/13] target/arm: Allow access to SPSR_hyp from hyp mode

[Richard Henderson <richard.henderson@linaro.org>]

On 2/6/24 23:29, Peter Maydell wrote:
> Architecturally, the AArch32 MSR/MRS to/from banked register
> instructions are UNPREDICTABLE for attempts to access a banked
> register that the guest could access in a more direct way (e.g.
> using this insn to access r8_fiq when already in FIQ mode).  QEMU has
> chosen to UNDEF on all of these.
> 
> However, for the case of accessing SPSR_hyp from hyp mode, it turns
> out that real hardware permits this, with the same effect as if the
> guest had directly written to SPSR. Further, there is some
> guest code out there that assumes it can do this, because it
> happens to work on hardware: an example Cortex-R52 startup code
> fragment uses this, and it got copied into various other places,
> including Zephyr. Zephyr was fixed to not use this:
>   https://github.com/zephyrproject-rtos/zephyr/issues/47330
> but other examples are still out there, like the selftest
> binary for the MPS3-AN536.
> 
> For convenience of being able to run guest code, permit
> this UNPREDICTABLE access instead of UNDEFing it.
> 
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> Last time this came up I preferred the "keep QEMU behaviour
> as it is, try to get the guest code fixed" approach:
>   https://www.mail-archive.com/qemu-devel@nongnu.org/msg899970.html
> but as this is the second time I lean a bit more towards
> behaving like the hardware.
> ---
>   target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------
>   target/arm/tcg/translate.c | 19 +++++++++++------
>   2 files changed, 43 insertions(+), 19 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~