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Tue, 06 Feb 2024 13:46:37 -0800 (PST) Message-ID: <7f812de0-c343-4d77-97c0-7bd8349db76b@linaro.org> Date: Wed, 7 Feb 2024 07:46:33 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 04/13] target/arm: Allow access to SPSR_hyp from hyp mode Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20240206132931.38376-1-peter.maydell@linaro.org> <20240206132931.38376-5-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20240206132931.38376-5-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/6/24 23:29, Peter Maydell wrote: > Architecturally, the AArch32 MSR/MRS to/from banked register > instructions are UNPREDICTABLE for attempts to access a banked > register that the guest could access in a more direct way (e.g. > using this insn to access r8_fiq when already in FIQ mode). QEMU has > chosen to UNDEF on all of these. > > However, for the case of accessing SPSR_hyp from hyp mode, it turns > out that real hardware permits this, with the same effect as if the > guest had directly written to SPSR. Further, there is some > guest code out there that assumes it can do this, because it > happens to work on hardware: an example Cortex-R52 startup code > fragment uses this, and it got copied into various other places, > including Zephyr. Zephyr was fixed to not use this: > https://github.com/zephyrproject-rtos/zephyr/issues/47330 > but other examples are still out there, like the selftest > binary for the MPS3-AN536. > > For convenience of being able to run guest code, permit > this UNPREDICTABLE access instead of UNDEFing it. > > Signed-off-by: Peter Maydell > --- > Last time this came up I preferred the "keep QEMU behaviour > as it is, try to get the guest code fixed" approach: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg899970.html > but as this is the second time I lean a bit more towards > behaving like the hardware. > --- > target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------ > target/arm/tcg/translate.c | 19 +++++++++++------ > 2 files changed, 43 insertions(+), 19 deletions(-) Reviewed-by: Richard Henderson r~