From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Marcin Nowakowski <marcin.nowakowski@fungible.com>,
Aurelien Jarno <aurelien@aurel32.net>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Subject: Re: [PATCH] target/mips: enable GINVx support for I6400 and I6500
Date: Mon, 10 Jul 2023 12:42:55 +0200 [thread overview]
Message-ID: <7fb2aebe-dab1-dfbb-42f1-b884ee52607d@linaro.org> (raw)
In-Reply-To: <20230630072806.3093704-1-marcin.nowakowski@fungible.com>
On 30/6/23 09:28, Marcin Nowakowski wrote:
> GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores,
> so indicate that properly in CP0.Config5 register bits [16:15].
>
> Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
> ---
> target/mips/cpu-defs.c.inc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2023-07-10 10:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-30 7:28 [PATCH] target/mips: enable GINVx support for I6400 and I6500 Marcin Nowakowski
2023-07-10 10:42 ` Philippe Mathieu-Daudé [this message]
2023-07-10 12:58 ` Jiaxun Yang
2023-07-10 14:59 ` Philippe Mathieu-Daudé
2023-07-10 19:21 ` Philippe Mathieu-Daudé
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