From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Alireza Sanaee <alireza.sanaee@huawei.com>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org
Cc: linuxarm@huawei.com, peter.maydell@linaro.org,
richard.henderson@linaro.org,
shameerali.kolothum.thodi@huawei.com,
Jonathan.Cameron@Huawei.com, alex.bennee@linaro.org,
jiangkunkun@huawei.com
Subject: Re: [PATCH v4] target/arm/tcg: refine cache descriptions with a wrapper
Date: Tue, 3 Sep 2024 15:18:41 +0200 [thread overview]
Message-ID: <7fda2f7c-091f-4b8b-bd61-5f8fcbbcf8ba@linaro.org> (raw)
In-Reply-To: <20240903083520.209-1-alireza.sanaee@huawei.com>
On 3/9/24 10:35, Alireza Sanaee wrote:
> This patch allows for easier manipulation of the cache description
> register, CCSIDR. Which is helpful for testing as well. Currently,
> numbers get hard-coded and might be prone to errors.
>
> Therefore, this patch adds a wrapper for different types of CPUs
> available in tcg to decribe caches. One function `make_ccsidr` supports
> two cases by carrying a parameter as FORMAT that can be LEGACY and
> CCIDX which determines the specification of the register.
>
> For CCSIDR register, 32 bit version follows specification [1].
> Conversely, 64 bit version follows specification [2].
This is the commit description,
---
this part is not relevant in the git history and can go
(hopefully the maintainer can do that for you),
>
> Changes from v2 [3] -> v3:
>
> 1) add only one function instead of ccsidr32 and ccsidr64
> 2) use deposit32 and deposit64 in ccsidr function
>
> Chnages from v3 [4] -> v4:
> 1) Use only one variable in the make_ccsidr function.
> 2) Include qemu/host-utils.h to get is_power_of_2() declaration.
>
---
keeping these references,
> [1] B4.1.19, ARM Architecture Reference Manual ARMv7-A and ARMv7-R
> edition, https://developer.arm.com/documentation/ddi0406
> [2] D23.2.29, ARM Architecture Reference Manual for A-profile Architecture,
> https://developer.arm.com/documentation/ddi0487/latest/
---
and dropping these ones.
> [3] https://lore.kernel.org/qemu-devel/20240830184713.224-1-alireza.sanaee@huawei.com/
> [4] https://lore.kernel.org/qemu-devel/20240902203211.270-1-alireza.sanaee@huawei.com/
>
> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
> ---
> target/arm/cpu-features.h | 50 ++++++++++++++++++
> target/arm/cpu64.c | 19 ++++---
> target/arm/tcg/cpu64.c | 108 +++++++++++++++++++-------------------
> 3 files changed, 117 insertions(+), 60 deletions(-)
Thanks for the iterations.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2024-09-03 13:19 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-03 8:35 [PATCH v4] target/arm/tcg: refine cache descriptions with a wrapper Alireza Sanaee via
2024-09-03 13:18 ` Philippe Mathieu-Daudé [this message]
2024-09-03 14:58 ` Alireza Sanaee via
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