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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd36d3csm1765049f8f.36.2025.02.06.05.20.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Feb 2025 05:20:48 -0800 (PST) Message-ID: <800dcc1b-8bf6-48e5-843a-99e630d4b494@linaro.org> Date: Thu, 6 Feb 2025 14:20:47 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] hw/sd/sdhci: Set reset value of interrupt registers To: BALATON Zoltan Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Bernhard Beschow , Jamin Lin References: <20250115190422.5F0FA4E6030@zero.eik.bme.hu> <8cbad5be-e67b-46bd-9198-f7c90ad5ff56@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/2/25 13:49, BALATON Zoltan wrote: > On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote: >> On 15/1/25 20:04, BALATON Zoltan wrote: >>> The interrupt enable registers are not reset to 0 but some bits are >>> enabled on reset. At least some U-Boot versions seem to expect this >>> and not initialise these registers before expecting interrupts. The >>> numbers in this patch match what QorIQ P1022 has on reset and fix >>> U-Boot for this SoC and should not break other drivers that initialise >>> (and thus overwrite) these reset values. >>> >>> Signed-off-by: BALATON Zoltan >>> --- >>> I've also noticed that the work around marked with an XXX comment near >>> line 600 breaks the U-Boot I've tested so I need to disable it: >>> if ((s->sdmasysad % boundary_chk) == 0) { >>> -        page_aligned = true; >>> +//        page_aligned = true; >>> } >>> What should this hack fix and could it be now removed or somehow >>> restricted to cases where it's needed? >> >> Cc'ing Jamin for >> https://lore.kernel.org/qemu-devel/20241213031205.641009-2- >> jamin_lin@aspeedtech.com/ >> >>> >>> hw/sd/sdhci.c | 2 ++ >>>   1 file changed, 2 insertions(+) >>> >>> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c >>> index 58375483e3..88eb0bfcb2 100644 >>> --- a/hw/sd/sdhci.c >>> +++ b/hw/sd/sdhci.c >>> @@ -303,6 +303,8 @@ static void sdhci_reset(SDHCIState *s) >>>       s->data_count = 0; >>>       s->stopped_state = sdhc_not_stopped; >>>       s->pending_insert_state = false; >>> +    s->norintstsen = 0x013f; >>> +    s->errintstsen = 0x117f; >> >> I guess the problem is earlier: >> >>    /* >>     * Set all registers to 0. Capabilities/Version registers are not >> cleared >>     * and assumed to always preserve their value, given to them during >>     * initialization >>     */ >>    memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s- >> >sdmasysad); >> >> Not all registers have to be reset. > > Nothing seems to program those registers before reset but the reset > values are documented (for Freescale eSDHCI) to be the above so just not > zeroing them does not seem to be enough. Bernhard has similar patch in > his branch, not sure if he came up with that separately or took this > one. Do you have some docs on which regs should not be reset? The header precises what is being modeled here: * SD Association Host Standard Specification v2.0 controller emulation * * Datasheet: PartA2_SD_Host_Controller_Simplified_Specification_Ver2.00.pdf I can not see the reset values you mentioned there. What is wrong with adding a TYPE_FREESCALE_ESDHC, like the TYPE_IMX_USDHC / TYPE_S3C_SDHCI types? Then you can add your reset handler fixing your fields after sdhci_poweron_reset().