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From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Michael Rolnik <mrolnik@gmail.com>, qemu-devel@nongnu.org
Cc: thuth@redhat.com, me@xcancerberox.com.ar,
	richard.henderson@linaro.org,
	Sarah Harris <S.E.Harris@kent.ac.uk>,
	dovgaluk@ispras.ru, imammedo@redhat.com,
	aleksandar.m.mail@gmail.com
Subject: Re: [PATCH v41 01/21] target/avr: Add outward facing interfaces and core CPU logic
Date: Mon, 23 Mar 2020 16:55:34 +0100	[thread overview]
Message-ID: <80141c57-7fb7-6e95-4070-54f7cc23e166@redhat.com> (raw)
In-Reply-To: <20200118191416.19934-2-mrolnik@gmail.com>

Hi Michael,

On 1/18/20 8:13 PM, Michael Rolnik wrote:
> This includes:
> - CPU data structures
> - object model classes and functions
> - migration functions
> - GDB hooks
> 
> Co-developed-by: Michael Rolnik <mrolnik@gmail.com>
> Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk>
> Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
> Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk>
> Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
> Acked-by: Igor Mammedov <imammedo@redhat.com>
> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>   target/avr/cpu-param.h |  37 ++
>   target/avr/cpu-qom.h   |  54 +++
>   target/avr/cpu.h       | 258 +++++++++++++
>   target/avr/cpu.c       | 826 +++++++++++++++++++++++++++++++++++++++++
>   target/avr/gdbstub.c   |  84 +++++
>   target/avr/machine.c   | 121 ++++++
>   gdb-xml/avr-cpu.xml    |  49 +++
>   7 files changed, 1429 insertions(+)
>   create mode 100644 target/avr/cpu-param.h
>   create mode 100644 target/avr/cpu-qom.h
>   create mode 100644 target/avr/cpu.h
>   create mode 100644 target/avr/cpu.c
>   create mode 100644 target/avr/gdbstub.c
>   create mode 100644 target/avr/machine.c
>   create mode 100644 gdb-xml/avr-cpu.xml
> 
[...]> diff --git a/target/avr/cpu.c b/target/avr/cpu.c
> new file mode 100644
> index 0000000000..c74c5106fe
> --- /dev/null
> +++ b/target/avr/cpu.c
> @@ -0,0 +1,826 @@
> +/*
> + * QEMU AVR CPU
> + *
> + * Copyright (c) 2019 Michael Rolnik
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "qemu/qemu-print.h"
> +#include "exec/exec-all.h"
> +#include "cpu.h"
> +#include "disas/dis-asm.h"
> +
> +static void avr_cpu_set_pc(CPUState *cs, vaddr value)
> +{
> +    AVRCPU *cpu = AVR_CPU(cs);
> +
> +    cpu->env.pc_w = value / 2; /* internally PC points to words */
> +}
> +
> +static bool avr_cpu_has_work(CPUState *cs)
> +{
> +    AVRCPU *cpu = AVR_CPU(cs);
> +    CPUAVRState *env = &cpu->env;
> +
> +    return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
> +            && cpu_interrupts_enabled(env);
> +}
> +
> +static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
> +{
> +    AVRCPU *cpu = AVR_CPU(cs);
> +    CPUAVRState *env = &cpu->env;
> +
> +    env->pc_w = tb->pc / 2; /* internally PC points to words */
> +}
> +
> +static void avr_cpu_reset(CPUState *cs)
> +{
> +    AVRCPU *cpu = AVR_CPU(cs);
> +    AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
> +    CPUAVRState *env = &cpu->env;
> +
> +    mcc->parent_reset(cs);
> +
> +    env->pc_w = 0;
> +    env->sregI = 1;
> +    env->sregC = 0;
> +    env->sregZ = 0;
> +    env->sregN = 0;
> +    env->sregV = 0;
> +    env->sregS = 0;
> +    env->sregH = 0;
> +    env->sregT = 0;
> +
> +    env->rampD = 0;
> +    env->rampX = 0;
> +    env->rampY = 0;
> +    env->rampZ = 0;
> +    env->eind = 0;
> +    env->sp = 0;
> +
> +    env->skip = 0;
> +
> +    memset(env->r, 0, sizeof(env->r));
> +
> +    tlb_flush(cs);

Why are you calling tlb_flush() here?

> +}



  reply	other threads:[~2020-03-23 15:56 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-18 19:13 [PATCH v41 00/21] QEMU AVR 8 bit cores Michael Rolnik
2020-01-18 19:13 ` [PATCH v41 01/21] target/avr: Add outward facing interfaces and core CPU logic Michael Rolnik
2020-03-23 15:55   ` Philippe Mathieu-Daudé [this message]
2020-03-23 17:03     ` Michael Rolnik
2020-03-23 18:03       ` Richard Henderson
2020-03-23 19:19         ` Philippe Mathieu-Daudé
2020-03-23 20:14           ` Michael Rolnik
2020-04-12  9:14             ` Michael Rolnik
2020-04-15  6:25               ` Philippe Mathieu-Daudé
2020-01-18 19:13 ` [PATCH v41 02/21] target/avr: Add instruction helpers Michael Rolnik
2020-01-18 19:13 ` [PATCH v41 03/21] target/avr: Add instruction translation - Registers definition Michael Rolnik
2020-01-18 19:13 ` [PATCH v41 04/21] target/avr: Add instruction translation - Arithmetic and Logic Instructions Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 05/21] target/avr: Add instruction translation - Branch Instructions Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 06/21] target/avr: Add instruction translation - Data Transfer Instructions Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 07/21] target/avr: Add instruction translation - Bit and Bit-test Instructions Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 08/21] target/avr: Add instruction translation - MCU Control Instructions Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 09/21] target/avr: Add instruction translation - CPU main translation function Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 10/21] target/avr: Add instruction disassembly function Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 11/21] hw/avr: Add limited support for USART peripheral Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 12/21] hw/avr: Add limited support for 16 bit timer peripheral Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 13/21] hw/avr: Add dummy mask device Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 14/21] hw/avr: Add example board configuration Michael Rolnik
2020-01-21 16:36   ` Igor Mammedov
2020-01-21 17:03     ` Philippe Mathieu-Daudé
2020-01-18 19:14 ` [PATCH v41 15/21] target/avr: Add section about AVR into QEMU documentation Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 16/21] target/avr: Register AVR support with the rest of QEMU Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 17/21] target/avr: Add machine none test Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 18/21] target/avr: Update build system Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 19/21] target/avr: Add boot serial test Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 20/21] target/avr: Add Avocado test Michael Rolnik
2020-01-18 19:14 ` [PATCH v41 21/21] target/avr: Update MAINTAINERS file Michael Rolnik
2020-01-20 22:10 ` [PATCH v41 00/21] QEMU AVR 8 bit cores Philippe Mathieu-Daudé

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