From: Richard Henderson <richard.henderson@linaro.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>, qemu-devel@nongnu.org
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [PULL 00/41] MIPS patches for 2021-11-02
Date: Tue, 2 Nov 2021 19:23:33 -0400 [thread overview]
Message-ID: <8033456b-97c1-ca4a-50b8-26d212bd54d7@linaro.org> (raw)
In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org>
On 11/2/21 9:41 AM, Philippe Mathieu-Daudé wrote:
> The following changes since commit 844d6dfc3e48a8d404b03ea815868fd01c6f7317:
>
> Merge remote-tracking branch 'remotes/alex.williamson/tags/vfio-update-20211101.0' into staging (2021-11-02 07:25:59 -0400)
>
> are available in the Git repository at:
>
> https://github.com/philmd/qemu.git tags/mips-20211102
>
> for you to fetch changes up to 6f08c9c5316a80a049d4861eaac5844466ba3eba:
>
> Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too" (2021-11-02 14:35:22 +0100)
>
> ----------------------------------------------------------------
> MIPS patches queue
>
> - Fine-grained MAINTAINERS sections
> - Fix MSA MADDV.B / MSUBV.B opcodes
> - Convert MSA opcodes to decodetree
> - Correct Loongson-3A4000 MSAIR register
> - Do not accept ELF nanoMIPS binaries on linux-user
> - Use ISA instead of PCI interrupts in VT82C686 PCI device
>
> ----------------------------------------------------------------
>
> BALATON Zoltan (4):
> usb/uhci: Misc clean up
> usb/uhci: Disallow user creating a vt82c686-uhci-pci device
> usb/uhci: Replace pci_set_irq with qemu_set_irq
> hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts
>
> Philippe Mathieu-Daudé (37):
> MAINTAINERS: Add MIPS general architecture support entry
> MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware
> MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware
> target/mips: Fix MSA MADDV.B opcode
> target/mips: Fix MSA MSUBV.B opcode
> target/mips: Adjust style in msa_translate_init()
> target/mips: Use dup_const() to simplify
> target/mips: Have check_msa_access() return a boolean
> target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
> target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
> target/mips: Convert MSA LDI opcode to decodetree
> target/mips: Convert MSA I5 instruction format to decodetree
> target/mips: Convert MSA BIT instruction format to decodetree
> target/mips: Convert MSA SHF opcode to decodetree
> target/mips: Convert MSA I8 instruction format to decodetree
> target/mips: Convert MSA load/store instruction format to decodetree
> target/mips: Convert MSA 2RF instruction format to decodetree
> target/mips: Convert MSA FILL opcode to decodetree
> target/mips: Convert MSA 2R instruction format to decodetree
> target/mips: Convert MSA VEC instruction format to decodetree
> target/mips: Convert MSA 3RF instruction format to decodetree
> (DF_HALF)
> target/mips: Convert MSA 3RF instruction format to decodetree
> (DF_WORD)
> target/mips: Convert MSA 3R instruction format to decodetree (part
> 1/4)
> target/mips: Convert MSA 3R instruction format to decodetree (part
> 2/4)
> target/mips: Convert MSA 3R instruction format to decodetree (part
> 3/4)
> target/mips: Convert MSA 3R instruction format to decodetree (part
> 4/4)
> target/mips: Convert MSA ELM instruction format to decodetree
> target/mips: Convert MSA COPY_U opcode to decodetree
> target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
> target/mips: Convert MSA MOVE.V opcode to decodetree
> target/mips: Convert CFCMSA opcode to decodetree
> target/mips: Convert CTCMSA opcode to decodetree
> target/mips: Remove generic MSA opcode
> target/mips: Remove one MSA unnecessary decodetree overlap group
> target/mips: Fix Loongson-3A4000 MSAIR config register
> target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU
> Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too"
>
> hw/usb/hcd-uhci.h | 3 +-
> target/mips/tcg/msa.decode | 243 ++-
> hw/usb/hcd-uhci.c | 14 +-
> hw/usb/vt82c686-uhci-pci.c | 15 +
> linux-user/elfload.c | 2 -
> target/mips/tcg/msa_helper.c | 64 +-
> target/mips/tcg/msa_translate.c | 2743 +++++++------------------------
> target/mips/cpu-defs.c.inc | 2 +-
> MAINTAINERS | 37 +-
> 9 files changed, 957 insertions(+), 2166 deletions(-)
Applied, thanks.
r~
prev parent reply other threads:[~2021-11-02 23:30 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-02 13:41 [PULL 00/41] MIPS patches for 2021-11-02 Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 01/41] MAINTAINERS: Add MIPS general architecture support entry Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 02/41] MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 03/41] MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 04/41] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 05/41] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 06/41] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 07/41] target/mips: Use dup_const() to simplify Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 08/41] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 09/41] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 10/41] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 11/41] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 12/41] target/mips: Convert MSA I5 instruction format " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 13/41] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 14/41] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 15/41] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 16/41] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 17/41] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 18/41] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 19/41] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 20/41] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 21/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 22/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 23/41] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 24/41] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 25/41] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 26/41] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 27/41] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 28/41] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 29/41] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 30/41] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 31/41] target/mips: Convert CFCMSA " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 32/41] target/mips: Convert CTCMSA " Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 33/41] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 34/41] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 35/41] target/mips: Fix Loongson-3A4000 MSAIR config register Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 36/41] target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 37/41] usb/uhci: Misc clean up Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 38/41] usb/uhci: Disallow user creating a vt82c686-uhci-pci device Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 39/41] usb/uhci: Replace pci_set_irq with qemu_set_irq Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 40/41] hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts Philippe Mathieu-Daudé
2021-11-02 13:42 ` [PULL 41/41] Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too" Philippe Mathieu-Daudé
2021-11-02 23:23 ` Richard Henderson [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8033456b-97c1-ca4a-50b8-26d212bd54d7@linaro.org \
--to=richard.henderson@linaro.org \
--cc=aleksandar.rikalo@syrmia.com \
--cc=aurelien@aurel32.net \
--cc=f4bug@amsat.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).