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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459e0cd2c90sm295842275e9.17.2025.08.11.03.26.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Aug 2025 03:26:55 -0700 (PDT) Message-ID: <805a9a58-df34-4a0c-8613-1c7f22310170@linaro.org> Date: Mon, 11 Aug 2025 12:26:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC 00/11] hw/arm/smmuv3: Add initial support for Secure State To: Tao Tang , Pierrick Bouvier , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Eric Auger , Peter Maydell , Chen Baozi , smostafa@google.com, jean-philippe@linaro.org References: <20250806151134.365755-1-tangtao1634@phytium.com.cn> <2169e4b1-97d1-43c9-a512-5e6e25a562ad@phytium.com.cn> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <2169e4b1-97d1-43c9-a512-5e6e25a562ad@phytium.com.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/8/25 18:11, Tao Tang wrote: > > On 2025/8/7 05:28, Pierrick Bouvier wrote: >> On 8/6/25 8:11 AM, Tao Tang wrote: >>> Secure Translation Path: Since the TF-A SMMUv3 Test Engine does not >>> support QEMU, and no secure device assignment feature exists yet, I >>> created a custom platform device to test the secure translation flow. >>> To trigger the translation logic, I initiated MMIO writes to this >>> device from within Hafnium. The device's MMIO callback handler then >>> performed DMA accesses via its IOMMU region, exercising the secure >>> translation path. While SMMUv3 is typically used for PCIe on >>> physical SoCs, the architecture allows its use with platform devices >>> via a stream-id binding in the device tree. The test harness >>> required some non-standard modifications to decouple the SMMU from >>> its tight integration with PCIe. The code for this test device is >>> available for review at [3]. README.md with detailed instructions is >>> also provided. >>> >> >> I am not sure about the current policy in QEMU for test oriented >> devices, but it would be really useful to have something similar >> upstream (Note: it's out of the scope of this series). >> One challenge working with SMMU emulation is that reproducing setups >> and triggering specific code paths is hard to achieve, due to the >> indirect use of SMMU feature (through DMA) and the complex software >> stack usually involved. >> Having something upstream available to work on SMMU emulation, at >> least on device side, would be a great addition. >> >> Eric, Peter, is this something that would be acceptable to merge? This shouldn't be an issue, we already have some: $ git ls-files|fgrep testdev chardev/testdev.c docs/specs/pci-testdev.rst hw/hyperv/hyperv_testdev.c hw/misc/pc-testdev.c hw/misc/pci-testdev.c hw/tricore/tricore_testdevice.c > Looking ahead, my plan is to refactor the smmuv3-test platform device. > The goal is to make it self-contained within QEMU, removing the current > dependency on Hafnium to trigger its operations. I plan to submit this > as a separate RFC patch series in the next few days.