From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Gn9mr-0008JJ-Kj for qemu-devel@nongnu.org; Thu, 23 Nov 2006 03:18:25 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Gn9mp-0008IB-45 for qemu-devel@nongnu.org; Thu, 23 Nov 2006 03:18:25 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Gn9mo-0008I8-SO for qemu-devel@nongnu.org; Thu, 23 Nov 2006 03:18:22 -0500 Received: from [212.78.202.66] (helo=lmfilto02.st1.spray.net) by monty-python.gnu.org with esmtp (Exim 4.52) id 1Gn9mo-0000fO-IH for qemu-devel@nongnu.org; Thu, 23 Nov 2006 03:18:22 -0500 Received: from lmfilto02.st1.spray.net (localhost [127.0.0.1]) by lmfilto02-10027.st1.spray.net (Postfix) with ESMTP id 81FC615F7692 for ; Thu, 23 Nov 2006 08:05:54 +0000 (GMT) Received: from localhost (localhost [127.0.0.1]) by lmfilto02-10025.st1.spray.net (Postfix) with ESMTP id 54EC615F768C for ; Thu, 23 Nov 2006 08:05:54 +0000 (GMT) Received: from cmcodec04.st1.spray.net (localhost [127.0.0.1]) by cmcodec04.st1.spray.net (Postfix) with SMTP id 38A06CA583 for ; Thu, 23 Nov 2006 08:05:53 +0000 (GMT) From: "=?ISO-8859-1?Q? Torbj=F6rn=20Andersson?=" Message-ID: <80846442723677@lycos-europe.com> Mime-Version: 1.0 Subject: Re: Re: SV: [Qemu-devel] ARM CPSR and conditional instructions Date: Thu, 23 Nov 2006 08:05:53 +0000 Content-Type: multipart/mixed; boundary="=_NextPart_Lycos_23677808464428_ID" Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. --=_NextPart_Lycos_23677808464428_ID Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: quoted-printable We are currently debugging the situation and we are actually not sure abo= ut the real reason for our current situation. However, we have seen that the condition bits in CPSR differers compared = to one other arm instruction set simulator, running the same binary. This= indicate for us that there might be something wrong i QEMU (translate.c = op.c for ARM). However, it is not proven yet. However, our understanding for the situation would improve if the strateg= y for simulating the conditional execution of ARM instructions is underst= ood.=20 Is a conditional ARM instruction treated as a branch-point, an end marker= for a TB? If not, jumps qemu within a TB? =20 Is it possible to describe the strategy with a reasonable effort? I would= be very greatfull. /Torbj=F6rn > Fr=E5n: Wolfgang Schildbach > Till: qemu-devel@nongnu.org > Rubrik: Re: SV: [Qemu-devel] ARM CPSR and conditional instructions > Datum: Thu, 23 Nov 2006 08:43:50 +0100 > I very much doubt there is any problem with the CPSR. The ARM emulation= =20 > has correctly run hundreds of millions of instructions coming from many= =20 > different compilers and hand-written assembly. Can you be more precise = in=20 > what the effect is that you see? >=20 > - Wolfgang >=20 > qemu-devel-bounces+wolfgang.schildbach=3Dcodingtechnologies.com@nongnu.= org=20 > wrote on 22.11.2006 22:13:01: >=20 > > I?m sorry for spamming you mailing list with my duplicate posts. I=20 > > had some problems sending my mail.=20 > >=20 > > /Torbj=F6rn > >=20 > > Fr=E5n: qemu-devel-bounces+tobbe.tt_home.se=3Dspray.se@nongnu.org=20 > > [mailto:qemu-devel-bounces+tobbe.tt_home.se=3Dspray.se@nongnu.org] F=F6= r=20 > > Torbj=F6rn Andersson > > Skickat: den 21 november 2006 22:16 > > Till: qemu-devel@nongnu.org > > =C4mne: [Qemu-devel] ARM CPSR and conditional instructions > >=20 > > Hello qemu developers! > >=20 > > I=B4m using QEMU for some ARM debugging and I have som questions=20 > > regardning the CPSR register. I get the feeling that the CPSR=20 > > condition code bits, representing the results from the ALU, are not=20 > > maintained at all points. Is the JIT in QEMU tailored in any way=20 > > towards GCC output? (Resulting in issues with the output of other=20 > > compilers that make use of the conditional execution of instructions=20 > etc.) > >=20 > > What I want to do is to try to verify QEMU maintains the CPSR=20 > > register and if not fix it. However, it is not trivial identify=20 > > where the updates should be placed. The relationship between=20 > > translate.c and op.c is not trival I must say :) > > I would be happy I anyone here could give me some pointers on how=20 > > the updates of the CPSR register is done today and what the strategy > > is. I guess there are plenty of performance ideas here as in the rest= of=20 > qemu. > >=20 > > Does anyone have any reflection on this topic or can anyone give me=20 > > some pointers? > >=20 > > Torbj=F6rn > > _______________________________________________ > > Qemu-devel mailing list > > Qemu-devel@nongnu.org > > href=3Dhttp://lists.nongnu.org/mailman/listinfo/qemu-devel>http://lists= nongnu > .org/mailman/listinfo/qemu-devel >=20 >=20 > _______________________________________________ > Qemu-devel mailing list > Qemu-devel@nongnu.org > href=3Dhttp://lists.nongnu.org/mailman/listinfo/qemu-devel>http://lists= nongnu > .org/mailman/listinfo/qemu-devel K=E4rlek och hur mycket pengar? F=E5 svar idag om din morgondag! http://h= oroskop.spray.se/ --=_NextPart_Lycos_23677808464428_ID--