From: Thomas Huth <thuth@redhat.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
Alistair Francis <alistair23@gmail.com>,
Peter Maydell <peter.maydell@linaro.org>
Cc: Alistair Francis <alistair.francis@wdc.com>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PULL 00/63] riscv-to-apply queue
Date: Mon, 3 Aug 2020 19:53:00 +0200 [thread overview]
Message-ID: <808d1b49-c03c-6bc7-09e1-7028259bbef6@redhat.com> (raw)
In-Reply-To: <67c76bac-2416-9ace-a71b-ab56b864975b@c-sky.com>
On 30/06/2020 10.44, LIU Zhiwei wrote:
>
>
> On 2020/6/30 16:11, Thomas Huth wrote:
>> On 30/06/2020 08.56, LIU Zhiwei wrote:
>>>
>>>
>>> On 2020/6/29 6:51, Alistair Francis wrote:
>>>> On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell
>>>> <peter.maydell@linaro.org> wrote:
>>>>> On Fri, 26 Jun 2020 at 22:53, Alistair Francis
>>>>> <alistair.francis@wdc.com> wrote:
>>>>>> The following changes since commit
>>>>>> 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>>>>>>
>>>>>> Merge remote-tracking branch
>>>>>> 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging
>>>>>> (2020-06-26 18:22:36 +0100)
>>>>>>
>>>>>> are available in the Git repository at:
>>>>>>
>>>>>> git@github.com:alistair23/qemu.git
>>>>>> tags/pull-riscv-to-apply-20200626-1
>>>>>>
>>>>>> for you to fetch changes up to
>>>>>> b39d59434ea10649fdb9e0a339c30c76e38c5e17:
>>>>>>
>>>>>> target/riscv: configure and turn on vector extension from
>>>>>> command line (2020-06-26 14:22:15 -0700)
>>>>>>
>>>>>> ----------------------------------------------------------------
>>>>>> This PR contains two patches to improve PLIC support in QEMU.
>>>>>>
>>>>>> The rest of the PR is adding support for the v0.7.1 RISC-V vector
>>>>>> extensions. This is experimental support as the vector extensions are
>>>>>> still in a draft state.
>>>>>>
>>>>> Hi; I'm afraid this fails to build on PPC64 and s390x (ie
>>>>> our big-endian hosts):
>>> Hi Peter,
>>>
>>> Do you mean you built the patch set on PPC64 or s390x and got errors
>>> in the list? Or just a worry?
>> >
>>> I have built the patch set on Ubuntu 18.04 X86-64. I don't know which
>>> compile option
>>> will fails the compilation. If you compiled on Ubuntu x86-64, could
>>> you show me the
>>> compile option?
>>
>> The related code in your patch "target/riscv: add vector stride load
>> and store instructions" is in a "#ifdef HOST_WORDS_BIGENDIAN" section,
>> so of course this bug does not trigger on a x86 host. You could
>> temporarily turn the "#ifdef HOST_WORDS_BIGENDIAN" into a "#if 1" to
>> see whether you can then also reproduce the error on x86.
>>
> Yes. I can reproduce it in this way.
>>> As a note: I try to find a PPC64 for test, but I'm afraid it will be
>>> too later.
>>> Is there an available PPC64 machine in the community?
>>
>> Maybe the easiest way to test your code on a big endian machine, too,
>> is to get a github account, clone the QEMU repository there, and
>> enable Travis for that repo. Then your code gets built on some non-x86
>> architectures (including a big-endian s390x) as soon as you push it to
>> the repo (see .travis.yml for details).
>>
> Thanks very much. I will have a try.
>>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
>>>>> ‘vext_clear’:
>>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
>>>>> ‘vext_clear’:
>>>>> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
>>>>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>>>> memset(tail & ~(7ULL), 0, part1);
>>
>> You obviously must not use "&" with a pointer. I guess you have to
>> cast to "uintptr_t" and back, or think of some other smart way to fix
>> this.
>>
> Yes. That's the error. It build successfully after the cast.
I'm sorry, but the new code fails to compile on big endian 32-bit
targets, see https://gitlab.com/huth/qemu/-/jobs/667762754#L3434 :
/builds/huth/qemu/target/riscv/vector_helper.c: In function 'vext_clear':
/builds/huth/qemu/target/riscv/vector_helper.c:154:16: error: cast to
pointer from integer of different size [-Werror=int-to-pointer-cast]
memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1);
^
/builds/huth/qemu/target/riscv/vector_helper.c:155:16: error: cast to
pointer from integer of different size [-Werror=int-to-pointer-cast]
memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2);
^
cc1: all warnings being treated as errors
A quick work-around is maybe to replace "ULL" with simply "UL" ?
Thomas
next prev parent reply other threads:[~2020-08-03 17:54 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-26 21:43 [PULL 00/63] riscv-to-apply queue Alistair Francis
2020-06-26 21:43 ` [PULL 01/63] riscv: plic: Honour source priorities Alistair Francis
2020-06-26 21:43 ` [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls Alistair Francis
2020-06-26 22:01 ` Jessica Clarke
2020-06-26 21:58 ` Alistair Francis
2020-06-26 21:43 ` [PULL 03/63] target/riscv: add vector extension field in CPURISCVState Alistair Francis
2020-06-26 21:43 ` [PULL 04/63] target/riscv: implementation-defined constant parameters Alistair Francis
2020-06-26 21:43 ` [PULL 05/63] target/riscv: support vector extension csr Alistair Francis
2020-06-26 21:43 ` [PULL 06/63] target/riscv: add vector configure instruction Alistair Francis
2020-06-26 21:43 ` [PULL 07/63] target/riscv: add an internals.h header Alistair Francis
2020-06-26 21:43 ` [PULL 08/63] target/riscv: add vector stride load and store instructions Alistair Francis
2020-06-26 21:43 ` [PULL 09/63] target/riscv: add vector index " Alistair Francis
2020-06-26 21:43 ` [PULL 10/63] target/riscv: add fault-only-first unit stride load Alistair Francis
2020-06-26 21:43 ` [PULL 11/63] target/riscv: add vector amo operations Alistair Francis
2020-06-26 21:43 ` [PULL 12/63] target/riscv: vector single-width integer add and subtract Alistair Francis
2020-06-26 21:43 ` [PULL 13/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 14/63] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions Alistair Francis
2020-06-26 21:43 ` [PULL 15/63] target/riscv: vector bitwise logical instructions Alistair Francis
2020-06-26 21:43 ` [PULL 16/63] target/riscv: vector single-width bit shift instructions Alistair Francis
2020-06-26 21:43 ` [PULL 17/63] target/riscv: vector narrowing integer right " Alistair Francis
2020-06-26 21:43 ` [PULL 18/63] target/riscv: vector integer comparison instructions Alistair Francis
2020-06-26 21:43 ` [PULL 19/63] target/riscv: vector integer min/max instructions Alistair Francis
2020-06-26 21:43 ` [PULL 20/63] target/riscv: vector single-width integer multiply instructions Alistair Francis
2020-06-26 21:43 ` [PULL 21/63] target/riscv: vector integer divide instructions Alistair Francis
2020-06-26 21:43 ` [PULL 22/63] target/riscv: vector widening integer multiply instructions Alistair Francis
2020-06-26 21:43 ` [PULL 23/63] target/riscv: vector single-width integer multiply-add instructions Alistair Francis
2020-06-26 21:43 ` [PULL 24/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 25/63] target/riscv: vector integer merge and move instructions Alistair Francis
2020-06-26 21:43 ` [PULL 26/63] target/riscv: vector single-width saturating add and subtract Alistair Francis
2020-06-26 21:43 ` [PULL 27/63] target/riscv: vector single-width averaging " Alistair Francis
2020-06-26 21:43 ` [PULL 28/63] target/riscv: vector single-width fractional multiply with rounding and saturation Alistair Francis
2020-06-26 21:43 ` [PULL 29/63] target/riscv: vector widening saturating scaled multiply-add Alistair Francis
2020-06-26 21:43 ` [PULL 30/63] target/riscv: vector single-width scaling shift instructions Alistair Francis
2020-06-26 21:43 ` [PULL 31/63] target/riscv: vector narrowing fixed-point clip instructions Alistair Francis
2020-06-26 21:43 ` [PULL 32/63] target/riscv: vector single-width floating-point add/subtract instructions Alistair Francis
2020-06-26 21:43 ` [PULL 33/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 34/63] target/riscv: vector single-width floating-point multiply/divide instructions Alistair Francis
2020-06-26 21:43 ` [PULL 35/63] target/riscv: vector widening floating-point multiply Alistair Francis
2020-06-26 21:43 ` [PULL 36/63] target/riscv: vector single-width floating-point fused multiply-add instructions Alistair Francis
2020-06-26 21:43 ` [PULL 37/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 38/63] target/riscv: vector floating-point square-root instruction Alistair Francis
2020-06-26 21:43 ` [PULL 39/63] target/riscv: vector floating-point min/max instructions Alistair Francis
2020-06-26 21:43 ` [PULL 40/63] target/riscv: vector floating-point sign-injection instructions Alistair Francis
2020-06-26 21:43 ` [PULL 41/63] target/riscv: vector floating-point compare instructions Alistair Francis
2020-06-26 21:43 ` [PULL 42/63] target/riscv: vector floating-point classify instructions Alistair Francis
2020-06-26 21:43 ` [PULL 43/63] target/riscv: vector floating-point merge instructions Alistair Francis
2020-06-26 21:43 ` [PULL 44/63] target/riscv: vector floating-point/integer type-convert instructions Alistair Francis
2020-06-26 21:43 ` [PULL 45/63] target/riscv: widening " Alistair Francis
2020-06-26 21:43 ` [PULL 46/63] target/riscv: narrowing " Alistair Francis
2020-06-26 21:43 ` [PULL 47/63] target/riscv: vector single-width integer reduction instructions Alistair Francis
2020-06-26 21:43 ` [PULL 48/63] target/riscv: vector wideing " Alistair Francis
2020-06-26 21:43 ` [PULL 49/63] target/riscv: vector single-width floating-point " Alistair Francis
2020-06-26 21:43 ` [PULL 50/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 51/63] target/riscv: vector mask-register logical instructions Alistair Francis
2020-06-26 21:43 ` [PULL 52/63] target/riscv: vector mask population count vmpopc Alistair Francis
2020-06-26 21:44 ` [PULL 53/63] target/riscv: vmfirst find-first-set mask bit Alistair Francis
2020-06-26 21:44 ` [PULL 54/63] target/riscv: set-X-first " Alistair Francis
2020-06-26 21:44 ` [PULL 55/63] target/riscv: vector iota instruction Alistair Francis
2020-06-26 21:44 ` [PULL 56/63] target/riscv: vector element index instruction Alistair Francis
2020-06-26 21:44 ` [PULL 57/63] target/riscv: integer extract instruction Alistair Francis
2020-06-26 21:44 ` [PULL 58/63] target/riscv: integer scalar move instruction Alistair Francis
2020-06-26 21:44 ` [PULL 59/63] target/riscv: floating-point scalar move instructions Alistair Francis
2020-06-26 21:44 ` [PULL 60/63] target/riscv: vector slide instructions Alistair Francis
2020-06-26 21:44 ` [PULL 61/63] target/riscv: vector register gather instruction Alistair Francis
2020-06-26 21:44 ` [PULL 62/63] target/riscv: vector compress instruction Alistair Francis
2020-06-26 21:44 ` [PULL 63/63] target/riscv: configure and turn on vector extension from command line Alistair Francis
2020-06-26 22:38 ` [PULL 00/63] riscv-to-apply queue no-reply
2020-06-26 22:44 ` no-reply
2020-06-28 14:30 ` Peter Maydell
2020-06-28 22:51 ` Alistair Francis
2020-06-29 0:52 ` LIU Zhiwei
2020-06-30 6:56 ` LIU Zhiwei
2020-06-30 8:11 ` Thomas Huth
2020-06-30 8:44 ` LIU Zhiwei
2020-08-03 17:53 ` Thomas Huth [this message]
2020-08-03 18:00 ` Philippe Mathieu-Daudé
2020-08-03 18:11 ` Thomas Huth
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