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[174.21.76.141]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c819a622f0sm5192630a91.8.2024.06.23.12.56.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 23 Jun 2024 12:56:05 -0700 (PDT) Message-ID: <80b6c7dc-1a85-4ad0-b715-8ead8c1c0448@linaro.org> Date: Sun, 23 Jun 2024 12:56:03 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] target/m68k: pass alignment into TCG memory load/store routines To: BALATON Zoltan , Mark Cave-Ayland Cc: qemu-devel@nongnu.org, laurent@vivier.eu References: <20240623115704.315645-1-mark.cave-ayland@ilande.co.uk> <20240623115704.315645-3-mark.cave-ayland@ilande.co.uk> <9d74ba20-a17d-64fd-7203-e4d450f77472@eik.bme.hu> Content-Language: en-US From: Richard Henderson In-Reply-To: <9d74ba20-a17d-64fd-7203-e4d450f77472@eik.bme.hu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/23/24 08:23, BALATON Zoltan wrote: > On Sun, 23 Jun 2024, Mark Cave-Ayland wrote: >> Now that do_unaligned_access has been implemented for 68k CPUs, pass the required >> alignment into the TCG memory load/store routines. This allows the TCG memory core >> to generate an Address Error exception for unaligned memory accesses if required. >> >> Suggested-by: Laurent Vivier >> Signed-off-by: Mark Cave-Ayland >> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2165 >> --- >> target/m68k/translate.c | 18 +++++++++++++++--- >> 1 file changed, 15 insertions(+), 3 deletions(-) >> >> diff --git a/target/m68k/translate.c b/target/m68k/translate.c >> index 445966fb6a..661a7b4def 100644 >> --- a/target/m68k/translate.c >> +++ b/target/m68k/translate.c >> @@ -303,13 +303,18 @@ static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr, >>                             int sign, int index) >> { >>     TCGv tmp = tcg_temp_new_i32(); >> +    MemOp memop = opsize | (sign ? MO_SIGN : 0) | MO_TE; >> >>     switch (opsize) { >>     case OS_BYTE: >> +        tcg_gen_qemu_ld_tl(tmp, addr, index, memop); >> +        break; >>     case OS_WORD: >>     case OS_LONG: >> -        tcg_gen_qemu_ld_tl(tmp, addr, index, >> -                           opsize | (sign ? MO_SIGN : 0) | MO_TE); >> +        if (!m68k_feature(s->env, M68K_FEATURE_UNALIGNED_DATA)) { >> +            memop |= MO_ALIGN_2; >> +        } >> +        tcg_gen_qemu_ld_tl(tmp, addr, index, memop); > > You could swap the order of these so byte comes last and fall through to it from word/long > to avoid duplicated line. > > Maybe this answers my question about where it's restriced by CPU type. I wonder if this > check for M68K_FEATURE_UNALIGNED_DATA could be avoded here and done by checking it in init > and only set the unaligned method for CPUs that need it to not add overhead for most CPUs > that don't need it. No, there's no overhead in having the unaligned method present always. But swapping the order of case labels, or sinking the tcg_gen_qemu_ld_tl call below the switch, is a good idea. r~