From: Richard Henderson <richard.henderson@linaro.org>
To: Andrew Jones <ajones@ventanamicro.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bmeng.cn@gmail.com,
zong.li@sifive.com, liwei1518@gmail.com, cwshu@andestech.com,
dbarboza@ventanamicro.com, philmd@linaro.org
Subject: Re: [PATCH v2] target/riscv32: Fix masking of physical address
Date: Mon, 9 Sep 2024 08:46:39 -0700 [thread overview]
Message-ID: <80b90332-58dd-4ba6-95b6-171790239d80@linaro.org> (raw)
In-Reply-To: <20240909083241.43836-2-ajones@ventanamicro.com>
On 9/9/24 01:32, Andrew Jones wrote:
> C doesn't extend the sign bit for unsigned types since there isn't a
> sign bit to extend. This means a promotion of a u32 to a u64 results
> in the upper 32 bits of the u64 being zero. If that result is then
> used as a mask on another u64 the upper 32 bits will be cleared. rv32
> physical addresses may be up to 34 bits wide, so we don't want to
> clear the high bits while page aligning the address. The fix is to
> use hwaddr for the mask, which, even on rv32, is 64-bits wide.
>
> Fixes: af3fc195e3c8 ("target/riscv: Change the TLB page size depends on PMP entries.")
> Signed-off-by: Andrew Jones<ajones@ventanamicro.com>
> ---
> -v2: Switch from signed long to hwaddr
>
> target/riscv/cpu_helper.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2024-09-09 15:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-09 8:32 [PATCH v2] target/riscv32: Fix masking of physical address Andrew Jones
2024-09-09 15:46 ` Richard Henderson [this message]
2024-09-10 3:03 ` Alistair Francis
2024-09-10 3:46 ` Alistair Francis
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