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[176.184.10.225]) by smtp.gmail.com with ESMTPSA id k2-20020a170906158200b009870a805b3esm3658888ejd.224.2023.06.19.04.01.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Jun 2023 04:01:46 -0700 (PDT) Message-ID: <80bafa6e-77d0-184d-4798-207d13ab435d@linaro.org> Date: Mon, 19 Jun 2023 13:01:44 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: Emulation of 'System OFF' mode in ARM nRF51 SoCs Content-Language: en-US To: Chris Laplante , qemu-arm References: Cc: "qemu-devel@nongnu.org" From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philmd@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Chris, On 14/6/23 04:27, Chris Laplante wrote: > Hi all, > > I am working on improving nRF51 emulation. Specifically I want to implement the special "System OFF" mode. System OFF is a power saving mode. In this mode, the system can only be woken up by a reset or a handful of peripherals (most notably, GPIO via high/low level detection on configured pins). System reset is triggered upon wakeup. > > I've been digging into the QEMU mailing list and source code and have come to the conclusion that deep sleep and low power modes are not implemented. There seems to be support for turning off ARM CPU cores, e.g. as used by imx6_src.c. But that doesn't apply here because I only have one CPU. What problem are you getting with a single CPU? The "arm/arm-powerctl.h" API should work well. If you scheduled a timer, I expect it to awake your CPU on expiration. You can also use a QMP command to toggle a GPIO and trigger an IRQ. You can use the qtest API to test your code, see some tests in tests/qtest/ using: - qtest_set_irq_in() - qtest_qom_set_bool() for GPIO Regards, Phil. > So ultimately what I think I will try to implement is what the nRF51 reference manual calls "Emulated System OFF mode". From the reference manual: > > If the device is in debug interface mode, System OFF will be emulated to secure > that all required resources needed for debugging are available during System OFF... > Since the CPU is kept on in emulated System OFF mode, it is recommended > to add an infinite loop directly after entering System OFF, to prevent the CPU from > executing code that normally should not be executed. > > Does anyone have any guidance on how to implement this? I don't particularly care about fidelity. As long as a GPIO level trigger can break the CPU out of the infinite loop (which the reference manual tells users to add) and jump into the reset vector, it will be good enough for my use. I don't really care about masking out other interrupt sources, for example. > > Thanks, > Chris >