Re: [RFC PATCH] tests/qtest/stm32l4x5_usart: Avoid accessing NVIC via MMIO

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

On 9/1/25 16:11, Fabiano Rosas wrote:
> Philippe Mathieu-Daudé <philmd@linaro.org> writes:
> 
>> The STM32L4x5 SoC family use a ARM Cortex-M core. Such
>> core is architecturally tied with a NVIC (interrupt controller),
>> having the NVIC MMIO mapped in the core address space.
>>
>> When using the QTest accelerator, we don't emulate vCPU, only
>> a dummy is created. For now, QTest is only supposed to access
>> MMIO devices mapped on the main 'SysBus'. Thus it shouldn't
>> be able to access a NVIC MMIO region, because such region is
>> specific to a vCPU address space, which isn't available under
>> QTest.
>>
>> In order to avoid NVIC MMIO accesses, rather than checking
>> UART IRQs on the NVIC, intercept the UART IRQ and check for
>> raised/lowered events.
>>
>> The sysbus USART1 IRQ output is wired to EXTI #26 input.
>> Use qtest_irq_intercept_out_named() to intercept it, count
>> the events with qtest_get_irq_lowered_counter() and
>> qtest_get_irq_raised_counter().
>>
>> Remove the then unused check/clear_nvic_pending() methods.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> Based-on: <20241216141818.111255-7-gustavo.romero@linaro.org>
>> "tests/qtest: Add API functions to capture IRQ toggling"
>>
>> This patch is to fix the problem reported by Fabiano when
>> removing the &first_cpu global in qtest, see analysis in:
>> https://lore.kernel.org/qemu-devel/05820c9b-a683-4eb4-a836-e97aa708d5e5@linaro.org/
>>
>> Note, while writing that patch I noticed a problem with the
>> b-l475e-iot01a machine. In bl475e_init() somes output GPIOs
>> are wired twice. The EXTI outputs are passed to the SoC with
>> qdev_pass_gpios(), and few are re-wired to the various output
>> IRQ splitters. I'll open a GitLab issue so it can be cleared
>> later.
>> ---
>>   tests/qtest/stm32l4x5_usart-test.c | 33 +++++++-----------------------
> 
> What about these other ones?
> stm32l4x5_exti-test.c
> stm32l4x5_rcc-test.c

Same changes, but I'd like to get feedback on this approach first,
because we lose the NVIC coverage. If we want to keep testing it,
then we need to rework the qtest mmio API to somehow specify which
address space is to be used; or a new API to resolve a device
particular MR and access it, without using the current global
sysbus address space.