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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e38325esm2086132f8f.27.2025.01.09.07.25.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Jan 2025 07:25:06 -0800 (PST) Message-ID: <80c3d02f-30a2-4b60-ba58-c2db17d15a0c@linaro.org> Date: Thu, 9 Jan 2025 16:25:04 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH] tests/qtest/stm32l4x5_usart: Avoid accessing NVIC via MMIO To: Fabiano Rosas , qemu-devel@nongnu.org, Peter Maydell Cc: Laurent Vivier , Gustavo Romero , Samuel Tardieu , qemu-arm@nongnu.org, =?UTF-8?Q?Alex_Benn=C3=A9e?= , Thomas Huth , Paolo Bonzini References: <20250107192637.67683-1-philmd@linaro.org> <87wmf42fam.fsf@suse.de> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <87wmf42fam.fsf@suse.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/1/25 16:11, Fabiano Rosas wrote: > Philippe Mathieu-Daudé writes: > >> The STM32L4x5 SoC family use a ARM Cortex-M core. Such >> core is architecturally tied with a NVIC (interrupt controller), >> having the NVIC MMIO mapped in the core address space. >> >> When using the QTest accelerator, we don't emulate vCPU, only >> a dummy is created. For now, QTest is only supposed to access >> MMIO devices mapped on the main 'SysBus'. Thus it shouldn't >> be able to access a NVIC MMIO region, because such region is >> specific to a vCPU address space, which isn't available under >> QTest. >> >> In order to avoid NVIC MMIO accesses, rather than checking >> UART IRQs on the NVIC, intercept the UART IRQ and check for >> raised/lowered events. >> >> The sysbus USART1 IRQ output is wired to EXTI #26 input. >> Use qtest_irq_intercept_out_named() to intercept it, count >> the events with qtest_get_irq_lowered_counter() and >> qtest_get_irq_raised_counter(). >> >> Remove the then unused check/clear_nvic_pending() methods. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> Based-on: <20241216141818.111255-7-gustavo.romero@linaro.org> >> "tests/qtest: Add API functions to capture IRQ toggling" >> >> This patch is to fix the problem reported by Fabiano when >> removing the &first_cpu global in qtest, see analysis in: >> https://lore.kernel.org/qemu-devel/05820c9b-a683-4eb4-a836-e97aa708d5e5@linaro.org/ >> >> Note, while writing that patch I noticed a problem with the >> b-l475e-iot01a machine. In bl475e_init() somes output GPIOs >> are wired twice. The EXTI outputs are passed to the SoC with >> qdev_pass_gpios(), and few are re-wired to the various output >> IRQ splitters. I'll open a GitLab issue so it can be cleared >> later. >> --- >> tests/qtest/stm32l4x5_usart-test.c | 33 +++++++----------------------- > > What about these other ones? > stm32l4x5_exti-test.c > stm32l4x5_rcc-test.c Same changes, but I'd like to get feedback on this approach first, because we lose the NVIC coverage. If we want to keep testing it, then we need to rework the qtest mmio API to somehow specify which address space is to be used; or a new API to resolve a device particular MR and access it, without using the current global sysbus address space.