Re: [Qemu-devel] [PATCH v2 06/11] target/arm: Decode aa32 armv8.1 two reg and a scalar

[Richard Henderson <richard.henderson@linaro.org>]

On 01/15/2018 09:47 AM, Peter Maydell wrote:
> On 18 December 2017 at 17:24, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>  target/arm/translate.c | 38 +++++++++++++++++++++++++++++++++++---
>>  1 file changed, 35 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/arm/translate.c b/target/arm/translate.c
>> index a9587ae242..1a0b0eaced 100644
>> --- a/target/arm/translate.c
>> +++ b/target/arm/translate.c
>> @@ -6973,11 +6973,43 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
>>                          }
>>                          neon_store_reg64(cpu_V0, rd + pass);
>>                      }
>> +                    break;
>> +                case 14: /* VQRDMLAH scalar */
>> +                case 15: /* VQRDMLSH scalar */
>> +                    if (!arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) {
>> +                        return 1;
>> +                    }
>> +                    if (u && ((rd | rn) & 1)) {
>> +                        return 1;
>> +                    }
> 
> The pseudocode also has UNDEF if Q==1 && Vm<0> == 1 ....

Not for the indexed version, encoding A2.

> 
>> +                    tmp2 = neon_get_scalar(size, rm);
>> +                    for (pass = 0; pass < (u ? 4 : 2); pass++) {
>> +                        void (*fn)(TCGv_i32, TCGv_env, TCGv_i32,
>> +                                   TCGv_i32, TCGv_i32);
> 
> Can we define a typedef for this, please ?

What would you name it?


r~