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From: "Corvin Köhne" <C.Koehne@beckhoff.com>
To: "tomitamoeko@gmail.com" <tomitamoeko@gmail.com>,
	"clg@redhat.com" <clg@redhat.com>,
	"alex.williamson@redhat.com" <alex.williamson@redhat.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: Re: [PATCH 08/11] vfio/igd: Allow overriding GMS with 0xf0 to 0xfe on Gen9+
Date: Wed, 23 Apr 2025 07:13:22 +0000	[thread overview]
Message-ID: <80e220ac7819902dcc1bb6a1974016a1d791346f.camel@beckhoff.com> (raw)
In-Reply-To: <20250421163112.21316-9-tomitamoeko@gmail.com>

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On Tue, 2025-04-22 at 00:31 +0800, Tomita Moeko wrote:
> CAUTION: External Email!!
> On Gen9 and later IGD devices, GMS 0xf0 to 0xfe represents 4MB to 60MB
> pre-allocated memory size in 4MB increments. Allow users overriding
> GMS with these values.
> 
> Signed-off-by: Tomita Moeko <tomitamoeko@gmail.com>
> ---
>  hw/vfio/igd.c | 59 +++++++++++++++++++++++++++++++++++----------------
>  1 file changed, 41 insertions(+), 18 deletions(-)
> 
> diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c
> index e3ff86d0e6..b747fdfaeb 100644
> --- a/hw/vfio/igd.c
> +++ b/hw/vfio/igd.c
> @@ -387,6 +387,44 @@ static bool vfio_pci_igd_setup_lpc_bridge(VFIOPCIDevice
> *vdev, Error **errp)
>      return true;
>  }
>  
> +static bool vfio_pci_igd_override_gms(int gen, uint32_t gms, uint32_t *gmch)
> +{
> +    bool ret = false;
> +
> +    if (gen == -1) {
> +        error_report("x-igd-gms is not supported on this device");
> +    } else if (gen < 8) {
> +        if (gms <= 0x10) {
> +            *gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT);
> +            *gmch |= gms << IGD_GMCH_GEN6_GMS_SHIFT;
> +            ret = true;
> +        } else {
> +            error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms",
> "0~0x10");
> +        }
> +    } else if (gen == 8) {
> +        if ((gms <= 0x40)) {

nit: you can remove a parantheses pair.

> +            *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT);
> +            *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT;
> +            ret = true;
> +        } else {
> +            error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms",
> "0~0x40");
> +        }
> +    } else {
> +        /* 0x0  to 0x40: 32MB increments starting at 0MB */
> +        /* 0xf0 to 0xfe: 4MB increments starting at 4MB */
> +        if ((gms <= 0x40) || (gms >= 0xf0 && gms <= 0xfe)) {
> +            *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT);
> +            *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT;
> +            ret = true;
> +        } else {
> +            error_report(QERR_INVALID_PARAMETER_VALUE,
> +                         "x-igd-gms", "0~0x40 or 0xf0~0xfe");
> +        }
> +    }
> +
> +    return ret;
> +}
> +
>  #define IGD_GGC_MMIO_OFFSET     0x108040
>  #define IGD_BDSM_MMIO_OFFSET    0x1080C0
>  
> @@ -573,24 +611,9 @@ static bool vfio_pci_igd_config_quirk(VFIOPCIDevice
> *vdev, Error **errp)
>       * 32MiB. This option should only be used when the desired size cannot be
>       * set from DVMT Pre-Allocated option in host BIOS.
>       */
> -    if (vdev->igd_gms) {
> -        if (gen < 8) {
> -            if (vdev->igd_gms <= 0x10) {
> -                gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT);
> -                gmch |= vdev->igd_gms << IGD_GMCH_GEN6_GMS_SHIFT;
> -            } else {
> -                error_report(QERR_INVALID_PARAMETER_VALUE,
> -                             "x-igd-gms", "0~0x10");
> -            }
> -        } else {
> -            if (vdev->igd_gms <= 0x40) {
> -                gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT);
> -                gmch |= vdev->igd_gms << IGD_GMCH_GEN8_GMS_SHIFT;
> -            } else {
> -                error_report(QERR_INVALID_PARAMETER_VALUE,
> -                             "x-igd-gms", "0~0x40");
> -            }
> -        }
> +    if (vdev->igd_gms &&
> +        !vfio_pci_igd_override_gms(gen, vdev->igd_gms, &gmch)) {
> +        return false;
>      }
>  
>      gms_size = igd_stolen_memory_size(gen, gmch);

-- 
Kind regards,
Corvin

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  reply	other threads:[~2025-04-23  7:15 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-21 16:31 [PATCH 00/11] vfio/igd: Detect IGD by OpRegion and enable OpRegion automatically Tomita Moeko
2025-04-21 16:31 ` [PATCH 01/11] vfio/igd: Restrict legacy mode to Gen6-9 devices Tomita Moeko
2025-04-24 22:57   ` Alex Williamson
2025-04-21 16:31 ` [PATCH 02/11] vfio/igd: Always emulate ASLS (OpRegion) register Tomita Moeko
2025-04-21 16:31 ` [PATCH 03/11] vfio/igd: Detect IGD device by OpRegion Tomita Moeko
2025-04-23  6:54   ` Corvin Köhne
2025-04-28 15:23     ` Tomita Moeko
2025-04-24 22:57   ` Alex Williamson
2025-04-21 16:31 ` [PATCH 04/11] vfio/igd: Remove vfio_pci_igd_setup_opregion Tomita Moeko
2025-04-21 16:31 ` [PATCH 05/11] vfio/igd: Check vendor and device ID on GVT-g mdev Tomita Moeko
2025-04-21 16:31 ` [PATCH 06/11] vfio/igd: Enable OpRegion by default Tomita Moeko
2025-04-21 16:31 ` [PATCH 07/11] vfio/igd: Allow hotplugging with OpRegion enabled Tomita Moeko
2025-04-24 22:57   ` Alex Williamson
2025-04-28 15:18     ` Tomita Moeko
2025-04-21 16:31 ` [PATCH 08/11] vfio/igd: Allow overriding GMS with 0xf0 to 0xfe on Gen9+ Tomita Moeko
2025-04-23  7:13   ` Corvin Köhne [this message]
2025-04-21 16:31 ` [PATCH 09/11] vfio/igd: Only emulate GGC register when x-igd-gms is set Tomita Moeko
2025-04-21 16:31 ` [PATCH 10/11] vfio/igd: Remove generation limitation for IGD passthrough Tomita Moeko
2025-04-23  7:19   ` Corvin Köhne
2025-04-21 16:31 ` [PATCH 11/11] vfio/igd: Update IGD passthrough documentation Tomita Moeko
2025-04-23  7:21   ` Corvin Köhne

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