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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id m7sm443159wms.0.2021.07.05.09.57.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Jul 2021 09:57:43 -0700 (PDT) Subject: Re: [RFC PATCH 0/8] Derive XSAVE state component offsets from CPUID leaf 0xd where possible To: David Edmondson , qemu-devel@nongnu.org References: <20210705104632.2902400-1-david.edmondson@oracle.com> From: Paolo Bonzini Message-ID: <811b9dd2-1e9f-d0fc-d3cb-c95671ac09ea@redhat.com> Date: Mon, 5 Jul 2021 18:57:42 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210705104632.2902400-1-david.edmondson@oracle.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.442, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, Michael Roth , Marcelo Tosatti , Richard Henderson , Cameron Esfahani , babu.moger@amd.com, Roman Bolshakov Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 05/07/21 12:46, David Edmondson wrote: > The offset of XSAVE state components within the XSAVE state area is > currently hard-coded via reference to the X86XSaveArea structure. This > structure is accurate for Intel systems at the time of writing, but > incorrect for newer AMD systems, as the state component for protection > keys is located differently (offset 0x980 rather than offset 0xa80). > > For KVM and HVF, replace the hard-coding of the state component > offsets with data derived from CPUID leaf 0xd information. > > TCG still uses the X86XSaveArea structure, as there is no underlying > CPU to use in determining appropriate values. > > This is a replacement for the changes in > https://lore.kernel.org/r/20210520145647.3483809-1-david.edmondson@oracle.com, > which simply modifed the hard-coded offsets for AMD systems. > > Testing on HVF is minimal (it builds and, by observation, the XSAVE > state component offsets reported to a running VM are accurate on an > older Intel system). This looks great, thanks, so I am queuing it. Paolo > David Edmondson (8): > target/i386: Declare constants for XSAVE offsets > target/i386: Consolidate the X86XSaveArea offset checks > target/i386: Clarify the padding requirements of X86XSaveArea > target/i386: Pass buffer and length to XSAVE helper > target/i386: Make x86_ext_save_areas visible outside cpu.c > target/i386: Observe XSAVE state area offsets > target/i386: Populate x86_ext_save_areas offsets using cpuid where > possible > target/i386: Move X86XSaveArea into TCG > > target/i386/cpu.c | 18 +-- > target/i386/cpu.h | 41 ++---- > target/i386/hvf/hvf-cpu.c | 34 +++++ > target/i386/hvf/hvf.c | 3 +- > target/i386/hvf/x86hvf.c | 19 ++- > target/i386/kvm/kvm-cpu.c | 36 +++++ > target/i386/kvm/kvm.c | 52 +------ > target/i386/tcg/fpu_helper.c | 1 + > target/i386/tcg/tcg-cpu.c | 20 +++ > target/i386/tcg/tcg-cpu.h | 57 ++++++++ > target/i386/xsave_helper.c | 267 ++++++++++++++++++++++++++--------- > 11 files changed, 381 insertions(+), 167 deletions(-) >