From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HyZOz-00009m-UQ for qemu-devel@nongnu.org; Wed, 13 Jun 2007 16:25:13 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HyZOv-00009O-Iy for qemu-devel@nongnu.org; Wed, 13 Jun 2007 16:25:12 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HyZOv-00009L-DQ for qemu-devel@nongnu.org; Wed, 13 Jun 2007 16:25:09 -0400 Received: from py-out-1112.google.com ([64.233.166.177]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1HyZOv-0002hU-5B for qemu-devel@nongnu.org; Wed, 13 Jun 2007 16:25:09 -0400 Received: by py-out-1112.google.com with SMTP id y77so616214pyg for ; Wed, 13 Jun 2007 13:25:08 -0700 (PDT) Message-ID: <812074ac0706131325t578dfd5eiaa5836b160a24679@mail.gmail.com> Date: Wed, 13 Jun 2007 16:25:07 -0400 From: "Ryan Riley" MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline Subject: [Qemu-devel] CPUTLBEntry Question Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org I'm making some small changes to the TLB stuff in QEMU 0.9.0 (specifically, I'm only working with i386-softmmu) and have run into an odd question I'm hoping someone can answer for me. The CPUTLBEntry structure definition in cpu-defs.h looks like this... typedef struct CPUTLBEntry { /* bit 31 to TARGET_PAGE_BITS : virtual address bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io zone number bit 3 : indicates that the entry is invalid bit 2..0 : zero */ target_ulong addr_read; target_ulong addr_write; target_ulong addr_code; /* addend to virtual address to get physical address */ target_phys_addr_t addend; } CPUTLBEntry; If I change it to add another member, like so.. typedef struct CPUTLBEntry { /* bit 31 to TARGET_PAGE_BITS : virtual address bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io zone number bit 3 : indicates that the entry is invalid bit 2..0 : zero */ target_ulong addr_read; target_ulong addr_write; target_ulong addr_code; /* addend to virtual address to get physical address */ target_phys_addr_t addend; /* New member */ target_phys_addr_t blah; } CPUTLBEntry; then QEMU crashes on startup. (It also crashes if I put that blah entry on the beginning instead of the end.) I'm sure there's code somewhere that must be making assumptions about the size of TLB entry, but I'm at a loss for finding it. (I have noticed that the assembly code in softmmu_header.h indexes to the addend based on addr_read or addr_write, but adding a new member to the end of the structure shouldn't impact that, right?) If anyone has any insight, I would be very appreciative. Thanks Ryan