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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: Re: [PATCH 6/6] target/arm: Allow arm_cpu_tlb_fill_align optionally set CPUTLBEntryFull
Date: Mon, 30 Jun 2025 07:56:14 -0600	[thread overview]
Message-ID: <8141d048-42e5-4b79-a90d-0ef1857d5857@linaro.org> (raw)
In-Reply-To: <20250630130937.3487-7-philmd@linaro.org>

On 6/30/25 07:09, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/arm/tcg/tlb_helper.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
> index 23c72a99f5c..df04ef351d1 100644
> --- a/target/arm/tcg/tlb_helper.c
> +++ b/target/arm/tcg/tlb_helper.c
> @@ -349,7 +349,9 @@ bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr address,
>                                 &res, fi)) {
>           res.f.extra.arm.pte_attrs = res.cacheattrs.attrs;
>           res.f.extra.arm.shareability = res.cacheattrs.shareability;
> -        *out = res.f;
> +        if (out) {
> +            *out = res.f;
> +        }
>           return true;
>       }
>       if (probe) {

Why?  There's no other way to get the phys addr result.
Are you only calling this for the raise-exception side effect?


r~


  reply	other threads:[~2025-06-30 13:56 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-30 13:09 [PATCH 0/6] target/arm: Few accel cleanups Philippe Mathieu-Daudé
2025-06-30 13:09 ` [PATCH 1/6] target/arm: Only set CPU_INTERRUPT_EXITTB for TCG Philippe Mathieu-Daudé
2025-06-30 13:49   ` Richard Henderson
2025-06-30 16:48   ` Pierrick Bouvier
2025-06-30 13:09 ` [PATCH 2/6] target/arm: Only allow disabling NEON when using TCG Philippe Mathieu-Daudé
2025-06-30 13:51   ` Richard Henderson
2025-06-30 16:49   ` Pierrick Bouvier
2025-07-04 13:03   ` Peter Maydell
2025-07-04 13:17     ` Philippe Mathieu-Daudé
2025-07-04 13:32       ` Peter Maydell
2025-06-30 13:09 ` [PATCH 3/6] target/arm: Better describe PMU depends on TCG or HVF Philippe Mathieu-Daudé
2025-06-30 17:03   ` Pierrick Bouvier
2025-06-30 17:03   ` Pierrick Bouvier
2025-06-30 13:09 ` [PATCH 4/6] target/arm: Re-use arm_is_psci_call() in HVF Philippe Mathieu-Daudé
2025-06-30 13:52   ` Richard Henderson
2025-06-30 16:50   ` Pierrick Bouvier
2025-06-30 13:09 ` [PATCH 5/6] target/arm: Share ARM_PSCI_CALL trace event between TCG and HVF Philippe Mathieu-Daudé
2025-06-30 13:53   ` Richard Henderson
2025-06-30 15:36     ` Philippe Mathieu-Daudé
2025-06-30 16:53   ` Pierrick Bouvier
2025-07-04 13:14     ` Peter Maydell
2025-07-07 14:02       ` Stefan Hajnoczi
2025-07-07 14:12         ` Peter Maydell
2025-07-07 14:08       ` Daniel P. Berrangé
2025-06-30 13:09 ` [PATCH 6/6] target/arm: Allow arm_cpu_tlb_fill_align optionally set CPUTLBEntryFull Philippe Mathieu-Daudé
2025-06-30 13:56   ` Richard Henderson [this message]
2025-06-30 15:35     ` Philippe Mathieu-Daudé
2025-06-30 17:00   ` Pierrick Bouvier

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