From: Julia <midnight@trainwit.ch>
To: "Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org
Subject: Re: [PATCH 1/1] target/riscv: log guest errors when reserved bits are set in PTEs
Date: Mon, 03 Feb 2025 18:12:21 +1100 [thread overview]
Message-ID: <8149beba-66b1-4707-93f1-083b8bc5ece0@app.fastmail.com> (raw)
In-Reply-To: <b76bf940-ff55-4619-a9ae-fa65c47e864f@ventanamicro.com>
> This happens because 'pte' is a 'target_ulong' type that, for riscv32, will be
> interpreted as uint32_t while the FMT being used is PRIx64.
>
> You can fix it by using TARGET_FMT_lx instead of PRIx64:
>
I've sent a follow-up patch fixing these build errors, it builds on 32 & 64 bit on my system. Cheers
As for the Signed-off-by, I'd rather not, and the contributing guide does not require it.
Regards,
Julia
next prev parent reply other threads:[~2025-02-03 7:13 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-02 5:15 [PATCH 0/1] -----BEGIN SSH SIGNATURE----- julia
2025-02-02 5:15 ` [PATCH 1/1] target/riscv: log guest errors when reserved bits are set in PTEs julia
2025-02-02 22:04 ` Daniel Henrique Barboza
2025-02-03 7:12 ` Julia [this message]
2025-02-03 14:14 ` Alex Bennée
2025-02-03 14:15 ` Alex Bennée
2025-02-03 17:29 ` Daniel Henrique Barboza
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