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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id q77sm1357441ooq.15.2020.12.17.09.24.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Dec 2020 09:24:04 -0800 (PST) Subject: Re: [PATCH v2 10/17] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG To: Peter Maydell References: <20200605041733.415188-1-richard.henderson@linaro.org> <20200605041733.415188-11-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <817d21f6-6494-e7c7-5eca-037b04b64f9f@linaro.org> Date: Thu, 17 Dec 2020 11:24:01 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers , Stephen Long Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/25/20 11:50 AM, Peter Maydell wrote: > On Fri, 5 Jun 2020 at 05:17, Richard Henderson > wrote: >> >> These prctl fields are required for the function of MTE. >> >> Signed-off-by: Richard Henderson > > This API doesn't seem to be in the upstream kernel yet, right? It has finally landed in 5.10. Thus the long delay since my last revision. >> + /* >> + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. >> + * Note that the syscall values are consistent with hw. >> + */ >> + env->cp15.sctlr_el[1] = >> + deposit64(env->cp15.sctlr_el[1], 38, 2, >> + arg2 >> TARGET_PR_MTE_TCF_SHIFT); > > This actually will be per-thread since each linux-user thread has > its own CPU. You probably need to do something to make it be > inherited across clone and fork, though (assuming those are > the required semantics). FWIW, these are a per-thread quantities. >>From arch/arm64/kernel/mte.c: > void mte_thread_switch(struct task_struct *next) > { > if (!system_supports_mte()) > return; > > /* avoid expensive SCTLR_EL1 accesses if no change */ > if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0) > update_sctlr_el1_tcf0(next->thread.sctlr_tcf0); > update_gcr_el1_excl(next->thread.gcr_user_incl); > } I don't think I have to do anything special wrt fork/clone, as env->cp15 will get copied by our own cpu_copy(). r~