From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>,
"arikalo@gmail.com" <arikalo@gmail.com>
Cc: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"cfu@mips.com" <cfu@mips.com>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
Richard Henderson <richard.henderson@linaro.org>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [PATCH v2 5/8] Add micromips to P5600
Date: Thu, 24 Oct 2024 15:22:30 -0300 [thread overview]
Message-ID: <81879c74-f2e6-4672-85d0-b72bd4d0620e@linaro.org> (raw)
In-Reply-To: <AM9PR09MB4851B248008D8045D466EA0B84402@AM9PR09MB4851.eurprd09.prod.outlook.com>
Hi Aleksandar,
On 18/10/24 10:20, Aleksandar Rakic wrote:
> Add micromips to P5600.
>
> Cherry-picked d7bf2c2f7f2e03b55c6e9c57eec5c3e6207005a0
> from https://github.com/MIPS/gnutools-qemu
>
> Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
> Signed-off-by: Matthew Fortune <matthew.fortune@imgtec.com>
> Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
> ---
> target/mips/cpu-defs.c.inc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Please Cc maintainers:
$ ./scripts/get_maintainer.pl -f target/mips/cpu-defs.c.inc
"Philippe Mathieu-Daudé" <philmd@linaro.org> (odd fixer:MIPS TCG CPUs)
Aurelien Jarno <aurelien@aurel32.net> (reviewer:MIPS TCG CPUs)
Jiaxun Yang <jiaxun.yang@flygoat.com> (reviewer:MIPS TCG CPUs)
Aleksandar Rikalo <arikalo@gmail.com> (reviewer:MIPS TCG CPUs)
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index fbf787d8ce..9428ece220 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -462,7 +462,7 @@ const mips_def_t mips_defs[] =
> .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
> .SEGBITS = 32,
> .PABITS = 40,
> - .insn_flags = CPU_MIPS32R5,
> + .insn_flags = CPU_MIPS32R5 | ASE_MICROMIPS,
This doesn't make any sense, if the core has microMIPS then bits 14-15
of CP0_Config3 can't be zeroes (meaning "Only MIPS32 is implemented,
microMIPS not implemented").
Besides, looking at "MIPS32® P5600 Multiprocessing System Software
User’s Manual, Revision 01.60" -> 'Table 2.6 Field Descriptions for
Config3 Register', CP0_Config3_ISA is 0b00, described as:
Indicates the instruction set availability.
This bit is always 0 to indicate MIPS32.
What are you trying to achieve, which tests are you running?
> .mmu_type = MMU_TYPE_R4000,
> },
> {
prev parent reply other threads:[~2024-10-24 18:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-18 13:20 [PATCH v2 5/8] Add micromips to P5600 Aleksandar Rakic
2024-10-19 7:45 ` Aleksandar Rikalo
2024-10-24 18:22 ` Philippe Mathieu-Daudé [this message]
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