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Thu, 24 Oct 2024 11:22:34 -0700 (PDT) Message-ID: <81879c74-f2e6-4672-85d0-b72bd4d0620e@linaro.org> Date: Thu, 24 Oct 2024 15:22:30 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/8] Add micromips to P5600 To: Aleksandar Rakic , "arikalo@gmail.com" Cc: Djordje Todorovic , "qemu-devel@nongnu.org" , "cfu@mips.com" , "peter.maydell@linaro.org" , Richard Henderson , Jiaxun Yang , Aurelien Jarno References: Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=philmd@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Aleksandar, On 18/10/24 10:20, Aleksandar Rakic wrote: > Add micromips to P5600. > > Cherry-picked d7bf2c2f7f2e03b55c6e9c57eec5c3e6207005a0 > from https://github.com/MIPS/gnutools-qemu > > Signed-off-by: Faraz Shahbazker > Signed-off-by: Matthew Fortune > Signed-off-by: Aleksandar Rakic > --- > target/mips/cpu-defs.c.inc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Please Cc maintainers: $ ./scripts/get_maintainer.pl -f target/mips/cpu-defs.c.inc "Philippe Mathieu-Daudé" (odd fixer:MIPS TCG CPUs) Aurelien Jarno (reviewer:MIPS TCG CPUs) Jiaxun Yang (reviewer:MIPS TCG CPUs) Aleksandar Rikalo (reviewer:MIPS TCG CPUs) > diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc > index fbf787d8ce..9428ece220 100644 > --- a/target/mips/cpu-defs.c.inc > +++ b/target/mips/cpu-defs.c.inc > @@ -462,7 +462,7 @@ const mips_def_t mips_defs[] = > .CP1_fcr31_rw_bitmask = 0xFF83FFFF, > .SEGBITS = 32, > .PABITS = 40, > - .insn_flags = CPU_MIPS32R5, > + .insn_flags = CPU_MIPS32R5 | ASE_MICROMIPS, This doesn't make any sense, if the core has microMIPS then bits 14-15 of CP0_Config3 can't be zeroes (meaning "Only MIPS32 is implemented, microMIPS not implemented"). Besides, looking at "MIPS32® P5600 Multiprocessing System Software User’s Manual, Revision 01.60" -> 'Table 2.6 Field Descriptions for Config3 Register', CP0_Config3_ISA is 0b00, described as: Indicates the instruction set availability. This bit is always 0 to indicate MIPS32. What are you trying to achieve, which tests are you running? > .mmu_type = MMU_TYPE_R4000, > }, > {