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[176.184.39.152]) by smtp.gmail.com with ESMTPSA id h18-20020a5d6892000000b002f9bfac5baesm5329503wru.47.2023.04.21.15.42.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Apr 2023 15:42:46 -0700 (PDT) Message-ID: <81a260d8-b104-57c7-050d-8aa631149fa4@linaro.org> Date: Sat, 22 Apr 2023 00:42:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v2 07/54] tcg: Split out tcg_out_ext32s Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org References: <20230411010512.5375-1-richard.henderson@linaro.org> <20230411010512.5375-8-richard.henderson@linaro.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-3.297, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 22/4/23 00:38, Philippe Mathieu-Daudé wrote: > On 11/4/23 03:04, Richard Henderson wrote: >> We will need a backend interface for performing 32-bit sign-extend. >> Use it in tcg_reg_alloc_op in the meantime. >> >> Signed-off-by: Richard Henderson >> --- >>   tcg/tcg.c                        |  4 ++++ >>   tcg/aarch64/tcg-target.c.inc     |  9 +++++++-- >>   tcg/arm/tcg-target.c.inc         |  5 +++++ >>   tcg/i386/tcg-target.c.inc        |  5 +++-- >>   tcg/loongarch64/tcg-target.c.inc |  2 +- >>   tcg/mips/tcg-target.c.inc        | 12 +++++++++--- >>   tcg/ppc/tcg-target.c.inc         |  5 +++-- >>   tcg/riscv/tcg-target.c.inc       |  2 +- >>   tcg/s390x/tcg-target.c.inc       | 10 +++++----- >>   tcg/sparc64/tcg-target.c.inc     | 11 ++++++++--- >>   tcg/tci/tcg-target.c.inc         |  9 ++++++++- >>   11 files changed, 54 insertions(+), 20 deletions(-) > > > >> diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc >> index f55829e9ce..d7964734c3 100644 >> --- a/tcg/aarch64/tcg-target.c.inc >> +++ b/tcg/aarch64/tcg-target.c.inc >> @@ -1429,6 +1429,11 @@ static void tcg_out_ext16s(TCGContext *s, >> TCGType type, TCGReg rd, TCGReg rn) >>       tcg_out_sxt(s, type, MO_16, rd, rn); >>   } >> +static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) >> +{ >> +    tcg_out_sxt(s, TCG_TYPE_I64, MO_32, rd, rn); >> +} >> + >>   static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits, >>                                  TCGReg rd, TCGReg rn) >>   { >> @@ -2232,7 +2237,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode >> opc, >>       case INDEX_op_bswap32_i64: >>           tcg_out_rev(s, TCG_TYPE_I32, MO_32, a0, a1); >>           if (a2 & TCG_BSWAP_OS) { >> -            tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a0); >> +            tcg_out_ext32s(s, a0, a0); >>           } >>           break; >>       case INDEX_op_bswap32_i32: >> @@ -2251,7 +2256,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode >> opc, >>           break; >>       case INDEX_op_ext_i32_i64: >> -    case INDEX_op_ext32s_i64: >>           tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1); > > While here, maybe reuse the new helper (easier to read): > >             tcg_out_ext32s(s, a0, a1); Now I see you do that in tcg_out_exts_i32_i64() in 2 patches :) >>           break; >>       case INDEX_op_extu_i32_i64: >> @@ -2322,6 +2326,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode >> opc, >>       case INDEX_op_ext16s_i32: >>       case INDEX_op_ext16u_i64: >>       case INDEX_op_ext16u_i32: >> +    case INDEX_op_ext32s_i64: >>       default: >>           g_assert_not_reached(); >>       } > > Reviewed-by: Philippe Mathieu-Daudé >